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Message-ID: <20240220135121.22578-3-quic_jkona@quicinc.com>
Date: Tue, 20 Feb 2024 19:21:17 +0530
From: Jagadeesh Kona <quic_jkona@...cinc.com>
To: Bjorn Andersson <andersson@...nel.org>,
        Konrad Dybcio
	<konrad.dybcio@...aro.org>,
        Michael Turquette <mturquette@...libre.com>,
        Stephen Boyd <sboyd@...nel.org>, Rob Herring <robh@...nel.org>,
        "Krzysztof
 Kozlowski" <krzysztof.kozlowski+dt@...aro.org>,
        Conor Dooley
	<conor+dt@...nel.org>
CC: Vladimir Zapolskiy <vladimir.zapolskiy@...aro.org>,
        Jagadeesh Kona
	<quic_jkona@...cinc.com>,
        Taniya Das <quic_tdas@...cinc.com>, <linux-arm-msm@...r.kernel.org>,
        <linux-clk@...r.kernel.org>, <devicetree@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>, Ajit Pandey
	<quic_ajipan@...cinc.com>,
        Imran Shaik <quic_imrashai@...cinc.com>,
        "Satya
 Priya Kakitapalli" <quic_skakitap@...cinc.com>
Subject: [PATCH V2 2/6] clk: qcom: videocc-sm8550: Add support for videocc XO clk ares

Add support for videocc XO clk ares for consumer drivers to be
able to request for this reset.

Fixes: f53153a37969 ("clk: qcom: videocc-sm8550: Add video clock controller driver for SM8550")
Signed-off-by: Jagadeesh Kona <quic_jkona@...cinc.com>
---
 drivers/clk/qcom/videocc-sm8550.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/qcom/videocc-sm8550.c b/drivers/clk/qcom/videocc-sm8550.c
index d73f747d2474..3a19204a9063 100644
--- a/drivers/clk/qcom/videocc-sm8550.c
+++ b/drivers/clk/qcom/videocc-sm8550.c
@@ -380,6 +380,7 @@ static const struct qcom_reset_map video_cc_sm8550_resets[] = {
 	[CVP_VIDEO_CC_MVS1C_BCR] = { 0x8074 },
 	[VIDEO_CC_MVS0C_CLK_ARES] = { .reg = 0x8064, .bit = 2, .udelay = 1000 },
 	[VIDEO_CC_MVS1C_CLK_ARES] = { .reg = 0x8090, .bit = 2, .udelay = 1000 },
+	[VIDEO_CC_XO_CLK_ARES] = { .reg = 0x8124, .bit = 2, .udelay = 100 },
 };
 
 static const struct regmap_config video_cc_sm8550_regmap_config = {
-- 
2.43.0


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