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Message-Id: <20240221-mbly-clk-v7-3-31d4ce3630c3@bootlin.com> Date: Wed, 21 Feb 2024 19:22:11 +0100 From: Théo Lebrun <theo.lebrun@...tlin.com> To: Gregory CLEMENT <gregory.clement@...tlin.com>, Michael Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>, Rob Herring <robh+dt@...nel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>, Conor Dooley <conor+dt@...nel.org>, Thomas Bogendoerfer <tsbogend@...ha.franken.de>, Linus Walleij <linus.walleij@...aro.org>, Rafał Miłecki <rafal@...ecki.pl>, Philipp Zabel <p.zabel@...gutronix.de> Cc: Vladimir Kondratiev <vladimir.kondratiev@...ileye.com>, linux-mips@...r.kernel.org, linux-clk@...r.kernel.org, devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, Thomas Petazzoni <thomas.petazzoni@...tlin.com>, Tawfik Bayouk <tawfik.bayouk@...ileye.com>, linux-gpio@...r.kernel.org, Théo Lebrun <theo.lebrun@...tlin.com>, Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org> Subject: [PATCH v7 03/14] dt-bindings: clock: mobileye,eyeq5-clk: add bindings Add DT schema bindings for the EyeQ5 clock controller driver. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org> Signed-off-by: Théo Lebrun <theo.lebrun@...tlin.com> --- .../bindings/clock/mobileye,eyeq5-clk.yaml | 51 ++++++++++++++++++++++ include/dt-bindings/clock/mobileye,eyeq5-clk.h | 22 ++++++++++ 2 files changed, 73 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/mobileye,eyeq5-clk.yaml b/Documentation/devicetree/bindings/clock/mobileye,eyeq5-clk.yaml new file mode 100644 index 000000000000..2d4f2cde1e58 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/mobileye,eyeq5-clk.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/mobileye,eyeq5-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mobileye EyeQ5 clock controller + +description: + The EyeQ5 clock controller handles 10 read-only PLLs derived from the main + crystal clock. It also exposes one divider clock, a child of one of the PLLs. + Its registers live in a shared region called OLB. + +maintainers: + - Grégory Clement <gregory.clement@...tlin.com> + - Théo Lebrun <theo.lebrun@...tlin.com> + - Vladimir Kondratiev <vladimir.kondratiev@...ileye.com> + +properties: + compatible: + const: mobileye,eyeq5-clk + + reg: + maxItems: 2 + + reg-names: + items: + - const: plls + - const: ospi + + "#clock-cells": + const: 1 + + clocks: + maxItems: 1 + description: + Input parent clock to all PLLs. Expected to be the main crystal. + + clock-names: + items: + - const: ref + +required: + - compatible + - reg + - reg-names + - "#clock-cells" + - clocks + - clock-names + +additionalProperties: false diff --git a/include/dt-bindings/clock/mobileye,eyeq5-clk.h b/include/dt-bindings/clock/mobileye,eyeq5-clk.h new file mode 100644 index 000000000000..26d8930335e4 --- /dev/null +++ b/include/dt-bindings/clock/mobileye,eyeq5-clk.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2024 Mobileye Vision Technologies Ltd. + */ + +#ifndef _DT_BINDINGS_CLOCK_MOBILEYE_EYEQ5_CLK_H +#define _DT_BINDINGS_CLOCK_MOBILEYE_EYEQ5_CLK_H + +#define EQ5C_PLL_CPU 0 +#define EQ5C_PLL_VMP 1 +#define EQ5C_PLL_PMA 2 +#define EQ5C_PLL_VDI 3 +#define EQ5C_PLL_DDR0 4 +#define EQ5C_PLL_PCI 5 +#define EQ5C_PLL_PER 6 +#define EQ5C_PLL_PMAC 7 +#define EQ5C_PLL_MPC 8 +#define EQ5C_PLL_DDR1 9 + +#define EQ5C_DIV_OSPI 10 + +#endif -- 2.43.2
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