linux-kernel - Re: [PATCH v7] dt-bindings: mtd: spi-nor: add optional interrupts property

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Message-Id: <CZAQHXT016DW.GDDY3ZAKS4CJ@kernel.org>
Date: Wed, 21 Feb 2024 12:52:25 +0100
From: "Michael Walle" <mwalle@...nel.org>
To: "Pratyush Yadav" <pratyush@...nel.org>
Cc: "Josua Mayer" <josua@...id-run.com>, "Tudor Ambarus"
 <tudor.ambarus@...aro.org>, "Miquel Raynal" <miquel.raynal@...tlin.com>,
 "Richard Weinberger" <richard@....at>, "Vignesh Raghavendra"
 <vigneshr@...com>, "Rob Herring" <robh+dt@...nel.org>, "Krzysztof
 Kozlowski" <krzysztof.kozlowski+dt@...aro.org>, "Conor Dooley"
 <conor+dt@...nel.org>, <linux-mtd@...ts.infradead.org>, "Takahiro Kuwano"
 <tkuw584924@...il.com>, "Takahiro Kuwano" <Takahiro.Kuwano@...ineon.com>,
 "Yazan Shhady" <yazan.shhady@...id-run.com>, "Rob Herring"
 <robh@...nel.org>, <devicetree@...r.kernel.org>,
 <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v7] dt-bindings: mtd: spi-nor: add optional interrupts
 property

On Wed Feb 21, 2024 at 11:48 AM CET, Pratyush Yadav wrote:
> On Wed, Feb 21 2024, Michael Walle wrote:
>
> > [+ Takahiro]
> >
> > Hi,
> >
> > On Wed Feb 21, 2024 at 10:13 AM CET, Josua Mayer wrote:
> >> Hi,
> >>
> >> Am 21.02.24 um 09:27 schrieb Michael Walle:
> >> > Hi,
> >> >
> >> > On Mon Feb 19, 2024 at 3:41 PM CET, Josua Mayer wrote:
> >> >> Some spi flash memories have an interrupt signal which can be used for
> >> >> signalling on-chip events such as busy status or ecc errors to the host.
> >> > Do you have an example? Maybe one with a public datasheet?
> >>
> >> My example is Infineon S28HS512T, however datasheet download requires 
> >> user account.
> >>
> >> S26HS512T has interrupt line, too, and datasheet is downloadable without 
> >> registration:
> >> https://www.infineon.com/cms/en/product/memories/nor-flash/semper-nor-flash-family/semper-nor-flash/#!documents
> >
> > Thanks, as far as I can see, both are hyperbus flashes. I'm asking
> > because I'm not aware of any SPI NOR flash with an interrupt line. 
>
> I found this datasheet [0] for S28H flash family from Infineon on
> Google. These are SPI NOR flashes. In pinout you can see there is an
> INT# signal. The signal description says: "System Interrupt (INT#). When
> LOW, the device is indicating that an internal event has occurred."
> Further in section 4.1.1.5 "INT# Output" it says:
>
>     HL-T/HS-T supports INT# output pin to indicate to the host system
>     that an event has occurred within the flash device. The user can
>     configure the INT# output pin to transition to the active (LOW)
>     state when:
>
>     - 2-bit ECC error is detected
>     - 1-bit ECC error is detected
>     - Transitioning from the Busy to the Ready state
>
> [0] https://www.infineon.com/dgdl/Infineon-S28HS256T_S28HS512T_S28HS01GT_S28HL256T_S28HL512T_S28HL01GT_256-Mb_(32-MB)_512-Mb_(64-MB)_1-Gb_(128-MB)_HS-T_(1.8-V)_HL-T_(3.0-V)_Semper_Flash_with_Octal_Interface-DataSheet-v03_00-EN.pdf?fileId=8ac78c8c7d0d8da4017d0ee6bca96f97&da=t


Okay then,
Acked-by: Michael Walle <mwalle@...nel.org>

-michael

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