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Message-ID: <20240222181324.28242-21-fancer.lancer@gmail.com>
Date: Thu, 22 Feb 2024 21:13:05 +0300
From: Serge Semin <fancer.lancer@...il.com>
To: Michal Simek <michal.simek@....com>,
Alexander Stein <alexander.stein@...tq-group.com>,
Borislav Petkov <bp@...en8.de>,
Tony Luck <tony.luck@...el.com>,
James Morse <james.morse@....com>,
Mauro Carvalho Chehab <mchehab@...nel.org>,
Robert Richter <rric@...nel.org>
Cc: Serge Semin <fancer.lancer@...il.com>,
Punnaiah Choudary Kalluri <punnaiah.choudary.kalluri@...inx.com>,
Dinh Nguyen <dinguyen@...nel.org>,
Arnd Bergmann <arnd@...db.de>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
linux-arm-kernel@...ts.infradead.org,
linux-edac@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: [PATCH v5 20/20] EDAC/synopsys: Convert to using BIT/GENMASK/FIELD_x macros
Instead of using the very handy helpers denoted in the subject the driver
has been created with the open-coded {mask,shift} statements. It makes the
code bulky, prone to mistakes and much harder to read. Seeing there are
many places in the driver implementing the CSR fields get/set pattern use
the FIELD_GET()/FIELD_PREP() macros introduced in the kernel specifically
for that case. In addition use the BIT() and GENMASK() macros to generate
the CSR flags/masks. While at it unify the row, column, rank, bank and
bank group macros names to be having a suffix similar to the
snps_ecc_error_info structure fields name.
Signed-off-by: Serge Semin <fancer.lancer@...il.com>
---
drivers/edac/synopsys_edac.c | 137 +++++++++++++++++------------------
1 file changed, 67 insertions(+), 70 deletions(-)
diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c
index c46cee035c0d..f181cd7b4447 100644
--- a/drivers/edac/synopsys_edac.c
+++ b/drivers/edac/synopsys_edac.c
@@ -6,6 +6,8 @@
* Copyright (C) 2012 - 2014 Xilinx, Inc.
*/
+#include <linux/bitfield.h>
+#include <linux/bits.h>
#include <linux/edac.h>
#include <linux/module.h>
#include <linux/platform_device.h>
@@ -89,33 +91,29 @@
#define ZYNQMP_DDR_QOS_IRQ_DB_OFST 0x2020C
/* DDR Master register definitions */
-#define DDR_MSTR_DEV_CFG_MASK 0xC0000000
-#define DDR_MSTR_DEV_CFG_SHIFT 30
+#define DDR_MSTR_DEV_CFG_MASK GENMASK(31, 30)
#define DDR_MSTR_DEV_X4 0
#define DDR_MSTR_DEV_X8 1
#define DDR_MSTR_DEV_X16 2
#define DDR_MSTR_DEV_X32 3
-#define DDR_MSTR_BUSWIDTH_MASK 0x3000
-#define DDR_MSTR_BUSWIDTH_SHIFT 12
+#define DDR_MSTR_BUSWIDTH_MASK GENMASK(13, 12)
#define DDR_MSTR_BUSWIDTH_16 2
#define DDR_MSTR_BUSWIDTH_32 1
#define DDR_MSTR_BUSWIDTH_64 0
-#define DDR_MSTR_MEM_LPDDR4 0x20
-#define DDR_MSTR_MEM_DDR4 0x10
-#define DDR_MSTR_MEM_LPDDR3 0x8
-#define DDR_MSTR_MEM_DDR2 0x4
-#define DDR_MSTR_MEM_DDR3 0x1
+#define DDR_MSTR_MEM_LPDDR4 BIT(5)
+#define DDR_MSTR_MEM_DDR4 BIT(4)
+#define DDR_MSTR_MEM_LPDDR3 BIT(3)
+#define DDR_MSTR_MEM_DDR2 BIT(2)
+#define DDR_MSTR_MEM_DDR3 BIT(0)
/* ECC CFG0 register definitions */
-#define ECC_CFG0_MODE_MASK 0x7
+#define ECC_CFG0_MODE_MASK GENMASK(2, 0)
#define ECC_CFG0_MODE_SECDED 0x4
/* ECC status register definitions */
-#define ECC_STAT_UECNT_MASK 0xF0000
-#define ECC_STAT_UECNT_SHIFT 16
-#define ECC_STAT_CECNT_MASK 0xF00
-#define ECC_STAT_CECNT_SHIFT 8
-#define ECC_STAT_BITNUM_MASK 0x7F
+#define ECC_STAT_UE_MASK GENMASK(23, 16)
+#define ECC_STAT_CE_MASK GENMASK(15, 8)
+#define ECC_STAT_BITNUM_MASK GENMASK(6, 0)
/* ECC control/clear register definitions */
#define ECC_CTRL_CLR_CE_ERR BIT(0)
@@ -126,34 +124,26 @@
#define ECC_CTRL_EN_UE_IRQ BIT(9)
/* ECC error count register definitions */
-#define ECC_ERRCNT_UECNT_MASK 0xFFFF0000
-#define ECC_ERRCNT_UECNT_SHIFT 16
-#define ECC_ERRCNT_CECNT_MASK 0xFFFF
-
-/* ECC Corrected Error Register Mask and Shifts*/
-#define ECC_CEADDR0_RW_MASK 0x3FFFF
-#define ECC_CEADDR0_RNK_MASK BIT(24)
-#define ECC_CEADDR1_BNKGRP_MASK 0x3000000
-#define ECC_CEADDR1_BNKNR_MASK 0x70000
-#define ECC_CEADDR1_COL_MASK 0xFFF
-#define ECC_CEADDR1_BNKGRP_SHIFT 24
-#define ECC_CEADDR1_BNKNR_SHIFT 16
-
-/* ECC Poison register shifts */
-#define ECC_POISON0_RANK_SHIFT 24
-#define ECC_POISON0_RANK_MASK BIT(24)
-#define ECC_POISON0_COLUMN_SHIFT 0
-#define ECC_POISON0_COLUMN_MASK 0xFFF
-#define ECC_POISON1_BG_SHIFT 28
-#define ECC_POISON1_BG_MASK 0x30000000
-#define ECC_POISON1_BANKNR_SHIFT 24
-#define ECC_POISON1_BANKNR_MASK 0x7000000
-#define ECC_POISON1_ROW_SHIFT 0
-#define ECC_POISON1_ROW_MASK 0x3FFFF
+#define ECC_ERRCNT_UECNT_MASK GENMASK(31, 16)
+#define ECC_ERRCNT_CECNT_MASK GENMASK(15, 0)
+
+/* ECC Corrected Error register definitions */
+#define ECC_CEADDR0_RANK_MASK GENMASK(27, 24)
+#define ECC_CEADDR0_ROW_MASK GENMASK(17, 0)
+#define ECC_CEADDR1_BANKGRP_MASK GENMASK(25, 24)
+#define ECC_CEADDR1_BANK_MASK GENMASK(23, 16)
+#define ECC_CEADDR1_COL_MASK GENMASK(11, 0)
+
+/* ECC Poison register definitions */
+#define ECC_POISON0_RANK_MASK GENMASK(27, 24)
+#define ECC_POISON0_COL_MASK GENMASK(11, 0)
+#define ECC_POISON1_BANKGRP_MASK GENMASK(29, 28)
+#define ECC_POISON1_BANK_MASK GENMASK(26, 24)
+#define ECC_POISON1_ROW_MASK GENMASK(17, 0)
/* DDRC ECC CE & UE poison mask */
-#define ECC_CEPOISON_MASK 0x3
-#define ECC_UEPOISON_MASK 0x1
+#define ECC_CEPOISON_MASK GENMASK(1, 0)
+#define ECC_UEPOISON_MASK BIT(0)
/* DDRC Device config shifts/masks */
#define DDR_MAX_ROW_SHIFT 18
@@ -209,9 +199,9 @@
#define RANK_B0_BASE 6
/* ZynqMP DDR QOS Interrupt register definitions */
-#define ZYNQMP_DDR_QOS_UE_MASK 0x4
-#define ZYNQMP_DDR_QOS_CE_MASK 0x2
-#define ZYNQMP_DDR_QOS_IRQ_MASK 0x6
+#define ZYNQMP_DDR_QOS_UE_MASK BIT(2)
+#define ZYNQMP_DDR_QOS_CE_MASK BIT(1)
+#define ZYNQMP_DDR_QOS_IRQ_MASK (ZYNQMP_DDR_QOS_UE_MASK | ZYNQMP_DDR_QOS_CE_MASK)
/**
* struct snps_ecc_error_info - ECC error log information.
@@ -303,38 +293,40 @@ static int snps_get_error_info(struct snps_edac_priv *priv)
if (!regval)
return 1;
- p->ceinfo.bitpos = (regval & ECC_STAT_BITNUM_MASK);
+ p->ceinfo.bitpos = FIELD_GET(ECC_STAT_BITNUM_MASK, regval);
regval = readl(base + ECC_ERRCNT_OFST);
- p->ce_cnt = regval & ECC_ERRCNT_CECNT_MASK;
- p->ue_cnt = (regval & ECC_ERRCNT_UECNT_MASK) >> ECC_ERRCNT_UECNT_SHIFT;
+ p->ce_cnt = FIELD_GET(ECC_ERRCNT_CECNT_MASK, regval);
+ p->ue_cnt = FIELD_GET(ECC_ERRCNT_UECNT_MASK, regval);
if (!p->ce_cnt)
goto ue_err;
regval = readl(base + ECC_CEADDR0_OFST);
- p->ceinfo.row = (regval & ECC_CEADDR0_RW_MASK);
+ p->ceinfo.row = FIELD_GET(ECC_CEADDR0_ROW_MASK, regval);
+
regval = readl(base + ECC_CEADDR1_OFST);
- p->ceinfo.bank = (regval & ECC_CEADDR1_BNKNR_MASK) >>
- ECC_CEADDR1_BNKNR_SHIFT;
- p->ceinfo.bankgrp = (regval & ECC_CEADDR1_BNKGRP_MASK) >>
- ECC_CEADDR1_BNKGRP_SHIFT;
- p->ceinfo.col = (regval & ECC_CEADDR1_COL_MASK);
+ p->ceinfo.bank = FIELD_GET(ECC_CEADDR1_BANK_MASK, regval);
+ p->ceinfo.bankgrp = FIELD_GET(ECC_CEADDR1_BANKGRP_MASK, regval);
+ p->ceinfo.col = FIELD_GET(ECC_CEADDR1_COL_MASK, regval);
+
p->ceinfo.data = readl(base + ECC_CSYND0_OFST);
+
edac_dbg(2, "ECCCSYN0: 0x%08X ECCCSYN1: 0x%08X ECCCSYN2: 0x%08X\n",
readl(base + ECC_CSYND0_OFST), readl(base + ECC_CSYND1_OFST),
readl(base + ECC_CSYND2_OFST));
+
ue_err:
if (!p->ue_cnt)
goto out;
regval = readl(base + ECC_UEADDR0_OFST);
- p->ueinfo.row = (regval & ECC_CEADDR0_RW_MASK);
+ p->ueinfo.row = FIELD_GET(ECC_CEADDR0_ROW_MASK, regval);
+
regval = readl(base + ECC_UEADDR1_OFST);
- p->ueinfo.bankgrp = (regval & ECC_CEADDR1_BNKGRP_MASK) >>
- ECC_CEADDR1_BNKGRP_SHIFT;
- p->ueinfo.bank = (regval & ECC_CEADDR1_BNKNR_MASK) >>
- ECC_CEADDR1_BNKNR_SHIFT;
- p->ueinfo.col = (regval & ECC_CEADDR1_COL_MASK);
+ p->ueinfo.bankgrp = FIELD_GET(ECC_CEADDR1_BANKGRP_MASK, regval);
+ p->ueinfo.bank = FIELD_GET(ECC_CEADDR1_BANK_MASK, regval);
+ p->ueinfo.col = FIELD_GET(ECC_CEADDR1_COL_MASK, regval);
+
p->ueinfo.data = readl(base + ECC_UESYND0_OFST);
out:
spin_lock_irqsave(&priv->reglock, flags);
@@ -483,7 +475,7 @@ static enum dev_type snps_get_dtype(const void __iomem *base)
if (!(regval & DDR_MSTR_MEM_DDR4))
return DEV_UNKNOWN;
- regval = (regval & DDR_MSTR_DEV_CFG_MASK) >> DDR_MSTR_DEV_CFG_SHIFT;
+ regval = FIELD_GET(DDR_MSTR_DEV_CFG_MASK, regval);
switch (regval) {
case DDR_MSTR_DEV_X4:
return DEV_X4;
@@ -510,7 +502,8 @@ static bool snps_get_ecc_state(void __iomem *base)
{
u32 regval;
- regval = readl(base + ECC_CFG0_OFST) & ECC_CFG0_MODE_MASK;
+ regval = readl(base + ECC_CFG0_OFST);
+ regval = FIELD_GET(ECC_CFG0_MODE_MASK, regval);
return (regval == ECC_CFG0_MODE_SECDED);
}
@@ -697,13 +690,13 @@ static void snps_data_poison_setup(struct snps_edac_priv *priv)
if (priv->rank_shift[0])
rank = (hif_addr >> priv->rank_shift[0]) & BIT(0);
- regval = (rank << ECC_POISON0_RANK_SHIFT) & ECC_POISON0_RANK_MASK;
- regval |= (col << ECC_POISON0_COLUMN_SHIFT) & ECC_POISON0_COLUMN_MASK;
+ regval = FIELD_PREP(ECC_POISON0_RANK_MASK, rank) |
+ FIELD_PREP(ECC_POISON0_COL_MASK, col);
writel(regval, priv->baseaddr + ECC_POISON0_OFST);
- regval = (bankgrp << ECC_POISON1_BG_SHIFT) & ECC_POISON1_BG_MASK;
- regval |= (bank << ECC_POISON1_BANKNR_SHIFT) & ECC_POISON1_BANKNR_MASK;
- regval |= (row << ECC_POISON1_ROW_SHIFT) & ECC_POISON1_ROW_MASK;
+ regval = FIELD_PREP(ECC_POISON1_BANKGRP_MASK, bankgrp) |
+ FIELD_PREP(ECC_POISON1_BANK_MASK, bank) |
+ FIELD_PREP(ECC_POISON1_ROW_MASK, row);
writel(regval, priv->baseaddr + ECC_POISON1_OFST);
}
@@ -742,10 +735,14 @@ static ssize_t inject_data_poison_show(struct device *dev,
{
struct mem_ctl_info *mci = to_mci(dev);
struct snps_edac_priv *priv = mci->pvt_info;
+ const char *errstr;
+ u32 regval;
+
+ regval = readl(priv->baseaddr + ECC_CFG1_OFST);
+ errstr = FIELD_GET(ECC_CEPOISON_MASK, regval) == ECC_CEPOISON_MASK ?
+ "Correctable Error" : "UnCorrectable Error";
- return sprintf(data, "Data Poisoning: %s\n\r",
- (((readl(priv->baseaddr + ECC_CFG1_OFST)) & 0x3) == 0x3)
- ? ("Correctable Error") : ("UnCorrectable Error"));
+ return sprintf(data, "Data Poisoning: %s\n\r", errstr);
}
static ssize_t inject_data_poison_store(struct device *dev,
@@ -852,7 +849,7 @@ static void snps_setup_column_address_map(struct snps_edac_priv *priv, u32 *addr
int index;
memtype = readl(priv->baseaddr + DDR_MSTR_OFST);
- width = (memtype & DDR_MSTR_BUSWIDTH_MASK) >> DDR_MSTR_BUSWIDTH_SHIFT;
+ width = FIELD_GET(DDR_MSTR_BUSWIDTH_MASK, memtype);
priv->col_shift[0] = 0;
priv->col_shift[1] = 1;
--
2.43.0
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