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Message-ID: <20240222053958.GF3374@thinkpad>
Date: Thu, 22 Feb 2024 11:09:58 +0530
From: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
To: Konrad Dybcio <konrad.dybcio@...aro.org>
Cc: Bjorn Andersson <andersson@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>,
cros-qcom-dts-watchers@...omium.org, linux-arm-msm@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 09/21] arm64: dts: qcom: sc8280xp: Add PCIe bridge node
On Wed, Feb 21, 2024 at 01:39:01PM +0100, Konrad Dybcio wrote:
> On 21.02.2024 04:41, Manivannan Sadhasivam wrote:
> > On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
> > for each controller instance. Hence, add a node to represent the bridge.
> >
> > While at it, let's remove the bridge properties from board dts as they are
> > now redundant.
> >
> > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
> > ---
> > .../dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 8 -----
> > arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 40 ++++++++++++++++++++++
> > 2 files changed, 40 insertions(+), 8 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
> > index def3976bd5bb..f0a0115e08fa 100644
> > --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
> > +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
> > @@ -733,14 +733,6 @@ &pcie4 {
> > status = "okay";
> >
> > pcie@0 {
> > - device_type = "pci";
> > - reg = <0x0 0x0 0x0 0x0 0x0>;
> > - #address-cells = <3>;
> > - #size-cells = <2>;
> > - ranges;
> > -
> > - bus-range = <0x01 0xff>;
> > -
> > wifi@0 {
>
> This doesn't seem right, pleas use a label
>
Why? A node label is useful if we want to reference it at the root level in
board dts, but here it is not.
- Mani
--
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