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Message-ID: <f01b2ad1fe239444148bded21ae4df64e3f267f2.camel@intel.com>
Date: Thu, 22 Feb 2024 11:49:52 +0000
From: "Huang, Kai" <kai.huang@...el.com>
To: "thomas.lendacky@....com" <thomas.lendacky@....com>, "dyoung@...hat.com"
<dyoung@...hat.com>, "bp@...en8.de" <bp@...en8.de>
CC: "Gao, Chao" <chao.gao@...el.com>, "luto@...nel.org" <luto@...nel.org>,
"Hansen, Dave" <dave.hansen@...el.com>, "x86@...nel.org" <x86@...nel.org>,
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<bhe@...hat.com>
Subject: Re: [PATCH 1/4] x86/coco: Add a new CC attribute to unify cache flush
during kexec
On Wed, 2024-02-21 at 10:28 +0100, Borislav Petkov wrote:
> On Tue, Feb 20, 2024 at 04:30:13PM -0600, Tom Lendacky wrote:
> > I believe the issues were that different Intel systems would hang or reset
> > and it was bisected to that commit that added the WBINVD. It was a while
> > ago, but I remember that they were similar to what the 1f5e7eb7868e commit
> > ended up fixing, which was debugged because sometimes the WBINVD was still
> > occasionally issued resulting in the following patch
> >
> > 9b040453d444 ("x86/smp: Dont access non-existing CPUID leaf")
> >
> > It just means that if we go to an unconditional WBINVD, then we need to be
> > careful.
>
> Let's try it.
>
> Dave, do you remember what issues
>
> f23d74f6c66c ("x86/mm: Rework wbinvd, hlt operation in stop_this_cpu()")
>
> fixed?
>
> If so, can you try the below diff ontop of latest tip/master to see if
> those issues would reappear?
>
> Thx.
>
> ---
>
> diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c
> index ab49ade31b0d..ec4dcc9f70ca 100644
> --- a/arch/x86/kernel/process.c
> +++ b/arch/x86/kernel/process.c
> @@ -824,8 +824,7 @@ void __noreturn stop_this_cpu(void *dummy)
> * Test the CPUID bit directly because the machine might've cleared
> * X86_FEATURE_SME due to cmdline options.
> */
> - if (c->extended_cpuid_level >= 0x8000001f && (cpuid_eax(0x8000001f) & BIT(0)))
> - native_wbinvd();
> + native_wbinvd();
>
> /*
> * This brings a cache line back and dirties it, but
>
I really appreciate if Dave can help here.
I will also reach out to see whether there's anyone in Intel met this before.
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