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Message-Id: <20240222125059.13331-1-hchauhan@ventanamicro.com> Date: Thu, 22 Feb 2024 18:20:57 +0530 From: Himanshu Chauhan <hchauhan@...tanamicro.com> To: linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org Cc: paul.walmsley@...ive.com, palmer@...belt.com, aou@...s.berkeley.edu Subject: [RFC PATCH 0/2] Introduce support for hardware break/watchpoints This patchset adds support of hardware breakpoints and watchpoints in RISC-V architecture. The framework is built on top of perf subsystem and SBI debug trigger extension. Currently following features are not supported and are in works: - Ptrace support - Single stepping - Virtualization of debug triggers The SBI debug trigger extension proposal (Draft v6) can be found at: https://lists.riscv.org/g/sig-hypervisors/message/361 The Sdtrig ISA is part of RISC-V debug specification which can be found at: https://github.com/riscv/riscv-debug-spec Himanshu Chauhan (2): riscv: Add SBI debug trigger extension and function ids riscv: Introduce support for hardware break/watchpoints arch/riscv/Kconfig | 1 + arch/riscv/include/asm/hw_breakpoint.h | 327 ++++++++++++ arch/riscv/include/asm/kdebug.h | 3 +- arch/riscv/include/asm/sbi.h | 31 ++ arch/riscv/kernel/Makefile | 1 + arch/riscv/kernel/hw_breakpoint.c | 659 +++++++++++++++++++++++++ arch/riscv/kernel/traps.c | 6 + 7 files changed, 1027 insertions(+), 1 deletion(-) create mode 100644 arch/riscv/include/asm/hw_breakpoint.h create mode 100644 arch/riscv/kernel/hw_breakpoint.c -- 2.34.1
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