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Message-Id: <20240223162010.6884-1-ni_liqiang@126.com>
Date: Sat, 24 Feb 2024 00:20:10 +0800
From: "ni.liqiang" <ni_liqiang@....com>
To: will@...nel.org,
danielmentz@...gle.com
Cc: iommu@...ts.linux.dev,
jin.qi@....com.cn,
joro@...tes.org,
linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org,
ni.liqiang@....com.cn,
niliqiang.io@...il.com,
robin.murphy@....com
Subject: Re: [PATCH] drivers/iommu: Ensure that the queue base address is successfully written during SMMU initialization.
> (Disclaimer: I don't know what a CCG port is)
CCG(CXL Gateway) is a part of the CMN700 Coherent Mesh Network. It plays
a crucial role in facilitating cross-die access in a multi-chip system.
> Hmmm. The part that doesn't make sense to me here is that migrating between
> CPUs implies context-switching, and we have a DSB on that path in
> __switch_to(). So why would adding barriers to the driver help? Maybe it
> just changes the timing?
This is very likely. Through our experiments, adding a delay before CMDQEN
does not reproduce the failure of writing to the CMDQ base register.
> I'm not sure what you're proposing, but I don't think Linux should be
> changed to accomodate this.
I am very grateful for the responses from both of you experts. We will
continue to check the current hardware configuration of the system
and attempt to fix this issue.
Once again, I express my thanks. Thank you.
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