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Message-ID: <alpine.DEB.2.21.2402261237260.60326@angie.orcam.me.uk>
Date: Mon, 26 Feb 2024 12:43:31 +0000 (GMT)
From: "Maciej W. Rozycki" <macro@...am.me.uk>
To: Ilpo Järvinen <ilpo.jarvinen@...ux.intel.com>
cc: Bjorn Helgaas <bhelgaas@...gle.com>, linux-pci@...r.kernel.org,
LKML <linux-kernel@...r.kernel.org>,
Mika Westerberg <mika.westerberg@...ux.intel.com>
Subject: Re: [PATCH 1/1] PCI: Cleanup link activation wait logic
On Fri, 16 Feb 2024, Ilpo Järvinen wrote:
> > > Yet another thing in this quirk code I don't like is how it can leaves the
> > > target speed to 2.5GT/s when the quirk fails to get the link working
> > > (which actually does happen in the disconnection cases because DLLLA won't
> > > be set so the target speed will not be restored).
> >
> > I chose to leave the target speed at the most recent setting, because the
> > link doesn't work in that case anyway, so I concluded it doesn't matter,
> > but reduces messing with the device; technically you should retrain again
> > afterwards. I'm not opposed to changing this if you have a use case.
>
> It remains suboptimally set in a case where something is plugged again
> into that port, for Thunderbolt it doesn't matter as the PCIe speed picked
> is quite bogus anyway, but disconnect then plug something again is not
> limited to Thunderbolt.
Sure, my understanding has been all PCIe option devices are supposed to
be hot-pluggable, at least these in the regular form factor (which is why
PCIe edge connector contacts have varying lengths, unlike conventional
PCI).
Maciej
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