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Message-ID: <CAMuHMdV3eVTek9sYwXbqu98ta8wx197GMc-k3q1RZRb8ar=jFg@mail.gmail.com>
Date: Mon, 26 Feb 2024 14:41:43 +0100
From: Geert Uytterhoeven <geert@...ux-m68k.org>
To: Prabhakar <prabhakar.csengg@...il.com>
Cc: Magnus Damm <magnus.damm@...il.com>, Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>, Conor Dooley <conor+dt@...nel.org>,
Catalin Marinas <catalin.marinas@....com>, Will Deacon <will@...nel.org>,
linux-arm-kernel@...ts.infradead.org, linux-renesas-soc@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
Fabrizio Castro <fabrizio.castro.jz@...esas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: Re: [PATCH 2/4] dt-bindings: arm: renesas: Document Renesas RZ/V2H{P}
System Controller
Hi Prabhakar,
Thanks for your patch!
On Mon, Feb 19, 2024 at 5:10 PM Prabhakar <prabhakar.csengg@...il.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
>
> Add DT binding documentation for System Controller (SYS) found on
> RZ/V2H{P} ("R9A09G057") SoC's.
RZ/V2H(P)
>
> SYS block contains the SYS_LSI_DEVID register which can be used to
> retrieve SoC version information.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@...esas.com>
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sysyaml
> @@ -0,0 +1,59 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/soc/renesas/renesas,r9a09g057-sys.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Renesas RZ/V2H{P} System Controller (SYS)
> +
> +maintainers:
> + - Geert Uytterhoeven <geert+renesas@...der.be>
> +
> +description:
> + The RZ/V2H{P} SYS (System Controller) controls the overall
RZ/V2H(P)
> + configuration of the LSI and supports the following functions,
> + - Trust zone control
> + - Extend access by specific masters to address beyond 4GB space
> + - GBETH configuration
> + - Control of settings and states of SRAM/PCIe/CM33/CA55/CR8/xSPI/ADC/TSU
> + - LSI version
> + - WDT stop control
> + - General registers
> +
> +properties:
> + compatible:
> + const: renesas,r9a09g057-sys
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + items:
> + - description: Clock from external oscillator
Isn't this SYS_0_PCLK inside the CPG?
> +
> + resets:
> + items:
> + - description: SYS_0_PRESETN reset signal
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - resets
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + extal_clk: extal-clk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <24000000>;
> + };
> +
> + sys: system-controller@...30000 {
> + compatible = "renesas,r9a09g057-sys";
> + reg = <0x10430000 0x10000>;
> + clocks = <&extal_clk>;
clocks = <&cpg 1>;
(I guess it will be 1 ;-)
> + resets = <&cpg 1>;
> + };
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68korg
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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