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Message-ID: <20240226190301.GN177224@ls.amr.corp.intel.com>
Date: Mon, 26 Feb 2024 11:03:01 -0800
From: Isaku Yamahata <isaku.yamahata@...ux.intel.com>
To: Binbin Wu <binbin.wu@...ux.intel.com>
Cc: isaku.yamahata@...el.com, kvm@...r.kernel.org,
	linux-kernel@...r.kernel.org, isaku.yamahata@...il.com,
	Paolo Bonzini <pbonzini@...hat.com>, erdemaktas@...gle.com,
	Sean Christopherson <seanjc@...gle.com>,
	Sagi Shahar <sagis@...gle.com>, Kai Huang <kai.huang@...el.com>,
	chen.bo@...el.com, hang.yuan@...el.com, tina.zhang@...el.com,
	Sean Christopherson <sean.j.christopherson@...el.com>,
	isaku.yamahata@...ux.intel.com
Subject: Re: [PATCH v18 039/121] KVM: x86/mmu: Track shadow MMIO value on a
 per-VM basis

On Sun, Jan 28, 2024 at 09:50:16PM +0800,
Binbin Wu <binbin.wu@...ux.intel.com> wrote:

> > diff --git a/arch/x86/kvm/mmu/spte.c b/arch/x86/kvm/mmu/spte.c
> > index 02a466de2991..318135daf685 100644
> > --- a/arch/x86/kvm/mmu/spte.c
> > +++ b/arch/x86/kvm/mmu/spte.c
> > @@ -74,10 +74,10 @@ u64 make_mmio_spte(struct kvm_vcpu *vcpu, u64 gfn, unsigned int access)
> >   	u64 spte = generation_mmio_spte_mask(gen);
> >   	u64 gpa = gfn << PAGE_SHIFT;
> > -	WARN_ON_ONCE(!shadow_mmio_value);
> > +	WARN_ON_ONCE(!vcpu->kvm->arch.shadow_mmio_value);
> >   	access &= shadow_mmio_access_mask;
> > -	spte |= shadow_mmio_value | access;
> > +	spte |= vcpu->kvm->arch.shadow_mmio_value | access;
> >   	spte |= gpa | shadow_nonpresent_or_rsvd_mask;
> >   	spte |= (gpa & shadow_nonpresent_or_rsvd_mask)
> >   		<< SHADOW_NONPRESENT_OR_RSVD_MASK_LEN;
> > @@ -411,6 +411,12 @@ void kvm_mmu_set_mmio_spte_mask(u64 mmio_value, u64 mmio_mask, u64 access_mask)
> >   }
> >   EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask);
> > +void kvm_mmu_set_mmio_spte_value(struct kvm *kvm, u64 mmio_value)
> > +{
> 
> Is it better to do some check on the mmio_value and warns if the value
> is illegal?

I don't think so because the only caller is kvm_mmu_set_mmio_spte_value(kvm, 0)
in tdx_vm_init().  I don't expect other caller.
-- 
Isaku Yamahata <isaku.yamahata@...ux.intel.com>

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