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Message-ID: <CANAwSgRmwXUqb-NUadgS1ENLvJQZXX9xjc4V6j+vw7jHf+dZZA@mail.gmail.com>
Date: Tue, 27 Feb 2024 18:33:51 +0530
From: Anand Moon <linux.amoon@...il.com>
To: Christian Hewitt <christianshewitt@...il.com>
Cc: Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>, Conor Dooley <conor+dt@...nel.org>,
Neil Armstrong <neil.armstrong@...aro.org>, Kevin Hilman <khilman@...libre.com>,
Jerome Brunet <jbrunet@...libre.com>,
Martin Blumenstingl <martin.blumenstingl@...glemail.com>,
devicetree <devicetree@...r.kernel.org>, linux-arm-kernel@...ts.infradead.org,
AML <linux-amlogic@...ts.infradead.org>, LKML <linux-kernel@...r.kernel.org>,
Viacheslav <adeep@...ina.in>
Subject: Re: [PATCHv1 3/5] arm64: dts: amlogic: Add cache information to the
Amlogic G12A SoCS
Hi Christian / Viacheslav,
On Tue, 6 Feb 2024 at 13:23, Christian Hewitt
<christianshewitt@...il.com> wrote:
>
> > On 6 Feb 2024, at 11:48 am, Viacheslav <adeep@...ina.in> wrote:
> >
> > You missed the AXG family with the Cortex-A53 CPU. The datasheet does not provide information on cache sizes. Given that the A113X/A113D are equipped with the Arm Cortex-A53 processor, it is assumed they use the same cache size as the S905/S905X/S905X2 models.
>
> GXM is also missing, and also using A53 cores.
>
> Christian
>
This patch is valid if the hardware supports perf PMU events, see below
I dont have the hardware.
Best way to let the Amlogic SoC members comment on the CPU L1/ /L2 cache size.
But with the lack of pref PMU events we cannot test this feature.
alarm@...hl-librecm ~]$ sudo perf list
List of pre-defined events (to be used in -e or -M):
branch-instructions OR branches [Hardware event]
branch-misses [Hardware event]
bus-cycles [Hardware event]
cache-misses [Hardware event]
cache-references [Hardware event]
cpu-cycles OR cycles [Hardware event]
instructions [Hardware event]
alignment-faults [Software event]
bpf-output [Software event]
cgroup-switches [Software event]
context-switches OR cs [Software event]
cpu-clock [Software event]
cpu-migrations OR migrations [Software event]
dummy [Software event]
emulation-faults [Software event]
major-faults [Software event]
minor-faults [Software event]
page-faults OR faults [Software event]
task-clock [Software event]
duration_time [Tool event]
user_time [Tool event]
system_time [Tool event]
armv8_cortex_a53:
L1-dcache-loads OR armv8_cortex_a53/L1-dcache-loads/
L1-dcache-load-misses OR armv8_cortex_a53/L1-dcache-load-misses/
L1-dcache-prefetch-misses OR armv8_cortex_a53/L1-dcache-prefetch-misses/
L1-icache-loads OR armv8_cortex_a53/L1-icache-loads/
L1-icache-load-misses OR armv8_cortex_a53/L1-icache-load-misses/
dTLB-load-misses OR armv8_cortex_a53/dTLB-load-misses/
iTLB-load-misses OR armv8_cortex_a53/iTLB-load-misses/
branch-loads OR armv8_cortex_a53/branch-loads/
branch-load-misses OR armv8_cortex_a53/branch-load-misses/
node-loads OR armv8_cortex_a53/node-loads/
node-stores OR armv8_cortex_a53/node-stores/
br_immed_retired OR armv8_cortex_a53/br_immed_retired/[Kernel PMU event]
br_mis_pred OR armv8_cortex_a53/br_mis_pred/ [Kernel PMU event]
br_pred OR armv8_cortex_a53/br_pred/ [Kernel PMU event]
bus_access OR armv8_cortex_a53/bus_access/ [Kernel PMU event]
bus_cycles OR armv8_cortex_a53/bus_cycles/ [Kernel PMU event]
cid_write_retired OR armv8_cortex_a53/cid_write_retired/[Kernel PMU event]
cpu_cycles OR armv8_cortex_a53/cpu_cycles/ [Kernel PMU event]
exc_return OR armv8_cortex_a53/exc_return/ [Kernel PMU event]
> >
> > Best regards,
> > --
> > Viacheslav Bocharov <adeep@...ina.in>
> >
> > _______________________________________________
> > linux-amlogic mailing list
> > linux-amlogic@...ts.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-amlogic
>
>
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