linux-kernel - [PATCH v5 4/5] dt-bindings: pci: layerscape-pci-ep: Add snps,dw-pcie-ep.yaml reference

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-Id: <20240228190321.580846-5-Frank.Li@nxp.com>
Date: Wed, 28 Feb 2024 14:03:20 -0500
From: Frank Li <Frank.Li@....com>
To: helgaas@...nel.org
Cc: Frank.Li@....com,
	bhelgaas@...gle.com,
	conor+dt@...nel.org,
	conor@...nel.org,
	devicetree@...r.kernel.org,
	imx@...ts.linux.dev,
	krzysztof.kozlowski+dt@...aro.org,
	kw@...ux.com,
	linux-kernel@...r.kernel.org,
	linux-pci@...r.kernel.org,
	lpieralisi@...nel.org,
	robh@...nel.org
Subject: [PATCH v5 4/5] dt-bindings: pci: layerscape-pci-ep: Add snps,dw-pcie-ep.yaml reference

Add snps,dw-pcie-ep.yaml.

Remove context that exist in snps,dw-pcie-ep.yaml.

Add an example for pcie-ep.

Signed-off-by: Frank Li <Frank.Li@....com>
---
 .../bindings/pci/fsl,layerscape-pcie-ep.yaml  | 54 ++++++++++---------
 1 file changed, 29 insertions(+), 25 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml
index 0af70a4bc5d91..e75b8853dca8c 100644
--- a/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml
+++ b/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml
@@ -10,8 +10,7 @@ maintainers:
   - Frank Li <Frank.Li@....com>
 
 description:
-  This PCIe RC controller is based on the Synopsys DesignWare PCIe IP
-  and thus inherits all the common properties defined in snps,dw-pcie.yaml.
+  This PCIe RC controller is based on the Synopsys DesignWare PCIe IP.
 
   This controller derives its clocks from the Reset Configuration Word (RCW)
   which is used to describe the PLL settings at the time of chip-reset.
@@ -35,31 +34,18 @@ properties:
       - const: fsl,ls-pcie-ep
 
   reg:
-    description: base addresses and lengths of the PCIe controller register blocks.
+    maxItems: 2
+
+  reg-names:
+    maxItems: 2
 
   interrupts:
-    description: A list of interrupt outputs of the controller. Must contain an
-      entry for each entry in the interrupt-names property.
+    minItems: 1
+    maxItems: 3
 
   interrupt-names:
     minItems: 1
     maxItems: 3
-    description: It could include the following entries.
-    items:
-      oneOf:
-        - description:
-            Used for interrupt line which reports AER events when
-            non MSI/MSI-X/INTx mode is used.
-          const: aer
-        - description:
-            Used for interrupt line which reports PME events when
-            non MSI/MSI-X/INTx mode is used.
-          const: pme
-        - description:
-            Used for SoCs(like ls2080a, lx2160a, ls2080a, ls2088a, ls1088a)
-            which has a single interrupt line for miscellaneous controller
-            events(could include AER and PME events).
-          const: intr
 
   fsl,pcie-scfg:
     $ref: /schemas/types.yaml#/definitions/phandle
@@ -68,10 +54,7 @@ properties:
       The second entry is the physical PCIe controller index starting from '0'.
       This is used to get SCFG PEXN registers
 
-  dma-coherent:
-    description: Indicates that the hardware IP block can ensure the coherency
-      of the data transferred from/to the IP block. This can avoid the software
-      cache flush/invalid actions, and improve the performance significantly
+  dma-coherent: true
 
   big-endian:
     $ref: /schemas/types.yaml#/definitions/flag
@@ -87,3 +70,24 @@ required:
   - fsl,pcie-scfg
   - dma-coherence
 
+allOf:
+  - $ref: /schemas/pci/snps,dw-pcie-ep.yaml#
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    soc {
+      #address-cells = <2>;
+      #size-cells = <2>;
+
+      pcie-ep@...0000 {
+        compatible = "fsl,ls1028a-pcie-ep", "fsl,ls-pcie-ep";
+        reg = <0x00 0x03400000 0x0 0x00100000
+              0x80 0x00000000 0x8 0x00000000>;
+        reg-names = "dbi", "addr_space";
+        interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
+        interrupt-names = "app";
+      };
+    };
+...
-- 
2.34.1