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Message-ID: <12f0b643-e2e8-8a9a-b264-5c7c460f1a24@oracle.com>
Date: Tue, 27 Feb 2024 20:43:03 -0800
From: Dongli Zhang <dongli.zhang@...cle.com>
To: Sean Christopherson <seanjc@...gle.com>,
        Paolo Bonzini <pbonzini@...hat.com>
Cc: kvm@...r.kernel.org, linux-kernel@...r.kernel.org,
        Yan Zhao <yan.y.zhao@...el.com>,
        Isaku Yamahata <isaku.yamahata@...el.com>,
        Michael Roth <michael.roth@....com>,
        Yu Zhang <yu.c.zhang@...ux.intel.com>,
        Chao Peng <chao.p.peng@...ux.intel.com>, Fuad Tabba <tabba@...gle.com>,
        David Matlack <dmatlack@...gle.com>
Subject: Re: [PATCH 03/16] KVM: x86: Define more SEV+ page fault error
 bits/flags for #NPF



On 2/27/24 18:41, Sean Christopherson wrote:
> Define more #NPF error code flags that are relevant to SEV+ (mostly SNP)
> guests, as specified by the APM:
> 
>  * Bit 34 (ENC):   Set to 1 if the guest’s effective C-bit was 1, 0 otherwise.
>  * Bit 35 (SIZEM): Set to 1 if the fault was caused by a size mismatch between
>                    PVALIDATE or RMPADJUST and the RMP, 0 otherwise.
>  * Bit 36 (VMPL):  Set to 1 if the fault was caused by a VMPL permission
>                    check failure, 0 otherwise.
>  * Bit 37 (SSS):   Set to VMPL permission mask SSS (bit 4) value if VmplSSS is
>                    enabled.

The above bits 34-37 do not match with the bits 31,34-36 in the patch.

Dongli Zhang

> 
> Note, the APM is *extremely* misleading, and strongly implies that the
> above flags can _only_ be set for #NPF exits from SNP guests.  That is a
> lie, as bit 34 (C-bit=1, i.e. was encrypted) can be set when running _any_
> flavor of SEV guest on SNP capable hardware.
> 
> Signed-off-by: Sean Christopherson <seanjc@...gle.com>
> ---
>  arch/x86/include/asm/kvm_host.h | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h
> index 88cc523bafa8..1e69743ef0fb 100644
> --- a/arch/x86/include/asm/kvm_host.h
> +++ b/arch/x86/include/asm/kvm_host.h
> @@ -261,8 +261,12 @@ enum x86_intercept_stage;
>  #define PFERR_FETCH_MASK	BIT(4)
>  #define PFERR_PK_MASK		BIT(5)
>  #define PFERR_SGX_MASK		BIT(15)
> +#define PFERR_GUEST_RMP_MASK	BIT_ULL(31)
>  #define PFERR_GUEST_FINAL_MASK	BIT_ULL(32)
>  #define PFERR_GUEST_PAGE_MASK	BIT_ULL(33)
> +#define PFERR_GUEST_ENC_MASK	BIT_ULL(34)
> +#define PFERR_GUEST_SIZEM_MASK	BIT_ULL(35)
> +#define PFERR_GUEST_VMPL_MASK	BIT_ULL(36)
>  #define PFERR_IMPLICIT_ACCESS	BIT_ULL(48)
>  
>  #define PFERR_NESTED_GUEST_PAGE (PFERR_GUEST_PAGE_MASK |	\

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