lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <8eb17d05ff857d154169e62b1f04413f@manjaro.org>
Date: Wed, 28 Feb 2024 11:42:25 +0100
From: Dragan Simic <dsimic@...jaro.org>
To: Anand Moon <linux.amoon@...il.com>
Cc: Rob Herring <robh+dt@...nel.org>, Krzysztof Kozlowski
 <krzysztof.kozlowski+dt@...aro.org>, Conor Dooley <conor+dt@...nel.org>,
 Heiko Stuebner <heiko@...ech.de>, devicetree@...r.kernel.org,
 linux-arm-kernel@...ts.infradead.org, linux-rockchip@...ts.infradead.org,
 linux-kernel@...r.kernel.org
Subject: Re: [PATCH v1] arm64: dts: rockchip: Add cache information to the
 Rockchip RK3566 and RK3568 SoC

Hello Anand,

On 2024-02-27 15:58, Dragan Simic wrote:
> On 2024-02-27 13:49, Anand Moon wrote:
>> On Tue, 27 Feb 2024 at 00:39, Dragan Simic <dsimic@...jaro.org> wrote:
>>> On 2024-02-26 19:23, Anand Moon wrote:
>>> > As per RK3568 Datasheet and TRM add missing cache information to
>>> > the Rockchip RK3566 and RK3568 SoC.
>>> >
>>> > - Each Cortex-A55 core has 32KB of L1 instruction cache available and
>>> >       32KB of L1 data cache available with ECC.
>>> > - Along with 512KB Unified L3 cache with ECC.
>>> >
>>> > With adding instruction cache and data cache and a write buffer to
>>> > reduce the effect of main memory bandwidth and latency on data
>>> > access performance.
>>> >
>>> > Signed-off-by: Anand Moon <linux.amoon@...il.com>
>>> 
>>> I was about to send my own patch that adds the same missing cache
>>> information, so please allow me to describe the proposed way to move
>>> forward.
>>> 
>>> The way I see it, your commit summary and description need a rather
>>> complete rewrite, to be more readable, more accurate, and to avoid
>>> including an irrelevant (and slightly misleading) description of the
>>> general role of caches.
>>> 
>>> Also, the changes to the dtsi file would benefit from small touch-ups
>>> here and there, for improved consistency, etc.
>>> 
>>> With all that in mind, I propose that you withdraw your patch and let
>>> me send my patch that will addresses all these issues, of course with
>>> a proper tag that lists you as a co-developer.  I think that would
>>> save us a fair amount of time going back and forth.
>>> 
>>> I hope you agree.
>> 
>> I have no issue with this,.If you have a better version plz share 
>> this.
> 
> Thank you, I'll send my patch within the next couple of days.

Here's a brief update...  Basically, not all of the cache-size values
found in your patch were correct, but I've got all of them calculated
again, double-checked, and cross-compared with the way values in my
earlier patch for the RK3399 SoC dtsi were calculated. [2]

It all checked out just fine.  It's all based on the RK3566 and RK3568
SoC datasheets and a couple of ARM specifications, which I'll describe
in detail in my patch description.  I'll send the patch after I test
it a bit, to make sure it all works as expected.

[1] 
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=b72633ba5cfa932405832de25d0f0a11716903b4

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ