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Message-ID: <ec835855-49f6-4b9a-9c58-e3fb90946c26@linaro.org>
Date: Thu, 29 Feb 2024 16:58:23 +0100
From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To: Frank Li <Frank.li@....com>
Cc: Vinod Koul <vkoul@...nel.org>, Rob Herring <robh@...nel.org>,
 Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
 Conor Dooley <conor+dt@...nel.org>, Peng Fan <peng.fan@....com>,
 imx@...ts.linux.dev, dmaengine@...r.kernel.org,
 linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
 Joy Zou <joy.zou@....com>
Subject: Re: [PATCH 4/5] dt-bindings: fsl-dma: fsl-edma: add fsl,imx8ulp-edma
 compatible string

On 29/02/2024 16:54, Frank Li wrote:
> On Thu, Feb 29, 2024 at 10:49:43AM +0100, Krzysztof Kozlowski wrote:
>> On 27/02/2024 18:21, Frank Li wrote:
>>>  
>>> +  - if:
>>> +      properties:
>>> +        compatible:
>>> +          contains:
>>> +            const: fsl,imx8ulp-edma
>>> +    then:
>>> +      properties:
>>> +        clock:
>>> +          maxItems: 33
>>> +        clock-names:
>>> +          items:
>>> +            - const: dma
>>> +            - pattern: "^CH[0-31]-clk$"
>>> +        interrupt-names: false
>>> +        interrupts:
>>> +          maxItems: 32
>>> +        "#dma-cells":
>>> +          const: 3
>>
>> Why suddenly fsl,vf610-edma can have from 2 to 33 clocks? Constrain
>> properly the variants.
> 
> Suppose you talk about 'fsl,imx8ulp-edma' instead 'fsl,vf610-edma'.
> 
> imx8ulp each channel have one clk, there are 32 channel. 1 channel for core
> controller. So max became 32.
> 
> I can add above information in commit message.

No, I meant Vybrid. Quick look at this code and the actual file suggest
that you allow vybrid with 30-whatever clocks. Test it.

Best regards,
Krzysztof


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