[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-Id:
<170924463463.14902.9593113600242840892.git-patchwork-notify@kernel.org>
Date: Thu, 29 Feb 2024 22:10:34 +0000
From: patchwork-bot+linux-riscv@...nel.org
To: Samuel Holland <samuel.holland@...ive.com>
Cc: linux-riscv@...ts.infradead.org, ajones@...tanamicro.com,
palmer@...belt.com, linux-kernel@...r.kernel.org, stable@...nel.org
Subject: Re: [PATCH -fixes 1/2] riscv: Fix enabling cbo.zero when running in
M-mode
Hello:
This series was applied to riscv/linux.git (fixes)
by Palmer Dabbelt <palmer@...osinc.com>:
On Sun, 11 Feb 2024 18:26:14 -0800 you wrote:
> When the kernel is running in M-mode, the CBZE bit must be set in the
> menvcfg CSR, not in senvcfg.
>
> Cc: stable@...nel.org
> Fixes: 43c16d51a19b ("RISC-V: Enable cbo.zero in usermode")
> Signed-off-by: Samuel Holland <samuel.holland@...ive.com>
>
> [...]
Here is the summary with links:
- [-fixes,1/2] riscv: Fix enabling cbo.zero when running in M-mode
https://git.kernel.org/riscv/c/3fb3f7164edc
- [-fixes,2/2] riscv: Save/restore envcfg CSR during CPU suspend
(no matching commit)
You are awesome, thank you!
--
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html
Powered by blists - more mailing lists