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Message-ID: <83ddabf1-e8a4-4870-a9bf-79aa45793056@intel.com>
Date: Thu, 29 Feb 2024 21:50:21 +0800
From: Xiaoyao Li <xiaoyao.li@...el.com>
To: Paolo Bonzini <pbonzini@...hat.com>, linux-kernel@...r.kernel.org,
 kvm@...r.kernel.org
Cc: seanjc@...gle.com, michael.roth@....com, isaku.yamahata@...el.com,
 thomas.lendacky@....com
Subject: Re: [PATCH 03/21] KVM: x86/mmu: Replace hardcoded value 0 for the
 initial value for SPTE

On 2/28/2024 7:20 AM, Paolo Bonzini wrote:
> From: Sean Christopherson <seanjc@...gle.com>
> 
> The TDX support will need the "suppress #VE" bit (bit 63) set as the
> initial value for SPTE.  To reduce code change size, introduce a new macro
> SHADOW_NONPRESENT_VALUE for the initial value for the shadow page table
> entry (SPTE) and replace hard-coded value 0 for it.  Initialize shadow page
> tables with their value.
> 
> The plan is to unconditionally set the "suppress #VE" bit for both AMD and
> Intel as: 1) AMD hardware uses the bit 63 as NX for present SPTE and
> ignored for non-present SPTE; 2) for conventional VMX guests, KVM never
> enables the "EPT-violation #VE" in VMCS control and "suppress #VE" bit is
> ignored by hardware.
> 
> Signed-off-by: Sean Christopherson <seanjc@...gle.com>
> Signed-off-by: Isaku Yamahata <isaku.yamahata@...el.com>
> Message-Id: <acdf09bf60cad12c495005bf3495c54f6b3069c9.1705965635.git.isaku.yamahata@...el.com>
> [Remove unnecessary CONFIG_X86_64 check. - Paolo]
> Signed-off-by: Paolo Bonzini <pbonzini@...hat.com>

Reviewed-by: Xiaoyao Li <xiaoyao.li@...el.com>


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