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Message-Id: <20240301185559.2661241-11-irogers@google.com>
Date: Fri, 1 Mar 2024 10:55:49 -0800
From: Ian Rogers <irogers@...gle.com>
To: Perry Taylor <perry.taylor@...el.com>, Samantha Alt <samantha.alt@...el.com>,
Caleb Biggers <caleb.biggers@...el.com>, Weilin Wang <weilin.wang@...el.com>,
Edward Baker <edward.baker@...el.com>, Peter Zijlstra <peterz@...radead.org>,
Ingo Molnar <mingo@...hat.com>, Arnaldo Carvalho de Melo <acme@...nel.org>, Namhyung Kim <namhyung@...nel.org>,
Mark Rutland <mark.rutland@....com>,
Alexander Shishkin <alexander.shishkin@...ux.intel.com>, Jiri Olsa <jolsa@...nel.org>,
Ian Rogers <irogers@...gle.com>, Adrian Hunter <adrian.hunter@...el.com>,
James Clark <james.clark@....com>, John Garry <john.g.garry@...cle.com>,
linux-perf-users@...r.kernel.org, linux-kernel@...r.kernel.org,
Stephane Eranian <eranian@...gle.com>
Subject: [PATCH v2 10/20] perf jevents: Add load store breakdown metrics ldst
for Intel
Give breakdown of number of instructions. Use the counter mask (cmask)
to show the number of cycles taken to retire the instructions.
Signed-off-by: Ian Rogers <irogers@...gle.com>
---
tools/perf/pmu-events/intel_metrics.py | 86 +++++++++++++++++++++++++-
1 file changed, 85 insertions(+), 1 deletion(-)
diff --git a/tools/perf/pmu-events/intel_metrics.py b/tools/perf/pmu-events/intel_metrics.py
index 9f42b489a81e..061914834cff 100755
--- a/tools/perf/pmu-events/intel_metrics.py
+++ b/tools/perf/pmu-events/intel_metrics.py
@@ -2,7 +2,7 @@
# SPDX-License-Identifier: (LGPL-2.1 OR BSD-2-Clause)
from metric import (d_ratio, has_event, max, CheckPmu, Event, JsonEncodeMetric,
JsonEncodeMetricGroupDescriptions, Literal, LoadEvents,
- Metric, MetricGroup, MetricRef, Select)
+ Metric, MetricConstraint, MetricGroup, MetricRef, Select)
import argparse
import json
import math
@@ -515,6 +515,89 @@ def IntelSwpf() -> Optional[MetricGroup]:
], description="Sofware prefetch instruction breakdown")
+def IntelLdSt() -> Optional[MetricGroup]:
+ if args.model in [
+ "bonnell",
+ "nehalemep",
+ "nehalemex",
+ "westmereep-dp",
+ "westmereep-sp",
+ "westmereex",
+ ]:
+ return None
+ LDST_LD = Event("MEM_INST_RETIRED.ALL_LOADS", "MEM_UOPS_RETIRED.ALL_LOADS")
+ LDST_ST = Event("MEM_INST_RETIRED.ALL_STORES", "MEM_UOPS_RETIRED.ALL_STORES")
+ LDST_LDC1 = Event(f"{LDST_LD.name}/cmask=1/")
+ LDST_STC1 = Event(f"{LDST_ST.name}/cmask=1/")
+ LDST_LDC2 = Event(f"{LDST_LD.name}/cmask=2/")
+ LDST_STC2 = Event(f"{LDST_ST.name}/cmask=2/")
+ LDST_LDC3 = Event(f"{LDST_LD.name}/cmask=3/")
+ LDST_STC3 = Event(f"{LDST_ST.name}/cmask=3/")
+ ins = Event("instructions")
+ LDST_CYC = Event("CPU_CLK_UNHALTED.THREAD",
+ "CPU_CLK_UNHALTED.CORE_P",
+ "CPU_CLK_UNHALTED.THREAD_P")
+ LDST_PRE = None
+ try:
+ LDST_PRE = Event("LOAD_HIT_PREFETCH.SWPF", "LOAD_HIT_PRE.SW_PF")
+ except:
+ pass
+ LDST_AT = None
+ try:
+ LDST_AT = Event("MEM_INST_RETIRED.LOCK_LOADS")
+ except:
+ pass
+ cyc = LDST_CYC
+
+ ld_rate = d_ratio(LDST_LD, interval_sec)
+ st_rate = d_ratio(LDST_ST, interval_sec)
+ pf_rate = d_ratio(LDST_PRE, interval_sec) if LDST_PRE else None
+ at_rate = d_ratio(LDST_AT, interval_sec) if LDST_AT else None
+
+ ldst_ret_constraint = MetricConstraint.GROUPED_EVENTS
+ if LDST_LD.name == "MEM_UOPS_RETIRED.ALL_LOADS":
+ ldst_ret_constraint = MetricConstraint.NO_GROUP_EVENTS_NMI
+
+ return MetricGroup("ldst", [
+ MetricGroup("ldst_total", [
+ Metric("ldst_total_loads", "Load/store instructions total loads",
+ ld_rate, "loads"),
+ Metric("ldst_total_stores", "Load/store instructions total stores",
+ st_rate, "stores"),
+ ]),
+ MetricGroup("ldst_prcnt", [
+ Metric("ldst_prcnt_loads", "Percent of all instructions that are loads",
+ d_ratio(LDST_LD, ins), "100%"),
+ Metric("ldst_prcnt_stores", "Percent of all instructions that are stores",
+ d_ratio(LDST_ST, ins), "100%"),
+ ]),
+ MetricGroup("ldst_ret_lds", [
+ Metric("ldst_ret_lds_1", "Retired loads in 1 cycle",
+ d_ratio(max(LDST_LDC1 - LDST_LDC2, 0), cyc), "100%",
+ constraint = ldst_ret_constraint),
+ Metric("ldst_ret_lds_2", "Retired loads in 2 cycles",
+ d_ratio(max(LDST_LDC2 - LDST_LDC3, 0), cyc), "100%",
+ constraint = ldst_ret_constraint),
+ Metric("ldst_ret_lds_3", "Retired loads in 3 or more cycles",
+ d_ratio(LDST_LDC3, cyc), "100%"),
+ ]),
+ MetricGroup("ldst_ret_sts", [
+ Metric("ldst_ret_sts_1", "Retired stores in 1 cycle",
+ d_ratio(max(LDST_STC1 - LDST_STC2, 0), cyc), "100%",
+ constraint = ldst_ret_constraint),
+ Metric("ldst_ret_sts_2", "Retired stores in 2 cycles",
+ d_ratio(max(LDST_STC2 - LDST_STC3, 0), cyc), "100%",
+ constraint = ldst_ret_constraint),
+ Metric("ldst_ret_sts_3", "Retired stores in 3 more cycles",
+ d_ratio(LDST_STC3, cyc), "100%"),
+ ]),
+ Metric("ldst_ld_hit_swpf", "Load hit software prefetches per second",
+ pf_rate, "swpf/s") if pf_rate else None,
+ Metric("ldst_atomic_lds", "Atomic loads per second",
+ at_rate, "loads/s") if at_rate else None,
+ ], description = "Breakdown of load/store instructions")
+
+
all_metrics = MetricGroup("", [
Idle(),
Rapl(),
@@ -522,6 +605,7 @@ all_metrics = MetricGroup("", [
Tsx(),
IntelBr(),
IntelL2(),
+ IntelLdSt(),
IntelPorts(),
IntelSwpf(),
])
--
2.44.0.278.ge034bb2e1d-goog
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