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Message-ID: <20240301-dreadful-discourse-6f1bb453d9c6@wendy>
Date: Fri, 1 Mar 2024 09:31:04 +0000
From: Conor Dooley <conor.dooley@...rochip.com>
To: Samuel Holland <samuel.holland@...ive.com>
CC: Palmer Dabbelt <palmer@...belt.com>, <linux-riscv@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>, <linux-mm@...ck.org>, Alexandre Ghiti
<alexghiti@...osinc.com>, Jisheng Zhang <jszhang@...nel.org>, Yunhui Cui
<cuiyunhui@...edance.com>
Subject: Re: [PATCH v5 00/13] riscv: ASID-related and UP-related TLB flush
enhancements
On Thu, Feb 29, 2024 at 03:21:41PM -0800, Samuel Holland wrote:
> Samuel Holland (13):
> riscv: Flush the instruction cache during SMP bringup
> riscv: Factor out page table TLB synchronization
From here onwards, fails on 32-bit, bunch of
implicit-function-declaration stuff.
> riscv: Use IPIs for remote cache/TLB flushes by default
> riscv: mm: Broadcast kernel TLB flushes only when needed
> riscv: Only send remote fences when some other CPU is online
> riscv: mm: Combine the SMP and UP TLB flush code
> riscv: Apply SiFive CIP-1200 workaround to single-ASID sfence.vma
> riscv: Avoid TLB flush loops when affected by SiFive CIP-1200
> riscv: mm: Introduce cntx2asid/cntx2version helper macros
> riscv: mm: Use a fixed layout for the MM context ID
> riscv: mm: Make asid_bits a local variable
> riscv: mm: Preserve global TLB entries when switching contexts
> riscv: mm: Always use an ASID to flush mm contexts
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