| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <20240301132936.621238-13-avromanov@salutedevices.com>
Date: Fri, 1 Mar 2024 16:29:27 +0300
From: Alexey Romanov <avromanov@...utedevices.com>
To: <neil.armstrong@...aro.org>, <clabbe@...libre.com>,
<herbert@...dor.apana.org.au>, <davem@...emloft.net>, <robh+dt@...nel.org>,
<krzysztof.kozlowski+dt@...aro.org>, <conor+dt@...nel.org>,
<khilman@...libre.com>, <jbrunet@...libre.com>,
<martin.blumenstingl@...glemail.com>, <vadim.fedorenko@...ux.dev>
CC: <linux-crypto@...r.kernel.org>, <linux-amlogic@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>, <kernel@...utedevices.com>, Alexey
Romanov <avromanov@...utedevices.com>
Subject: [PATCH v5 12/21] drivers: crypto: meson: add support for AES-CTR
This patch adds support for AES-CTR algorithm.
Tested via tcrypt and custom tests.
Signed-off-by: Alexey Romanov <avromanov@...utedevices.com>
---
drivers/crypto/amlogic/amlogic-gxl-cipher.c | 59 +++++++++++++++++++--
drivers/crypto/amlogic/amlogic-gxl-core.c | 1 +
drivers/crypto/amlogic/amlogic-gxl.h | 2 +
3 files changed, 58 insertions(+), 4 deletions(-)
diff --git a/drivers/crypto/amlogic/amlogic-gxl-cipher.c b/drivers/crypto/amlogic/amlogic-gxl-cipher.c
index 8b8f79f08d6e..698868fe2502 100644
--- a/drivers/crypto/amlogic/amlogic-gxl-cipher.c
+++ b/drivers/crypto/amlogic/amlogic-gxl-cipher.c
@@ -138,6 +138,15 @@ static void meson_unmap_scatterlist(struct skcipher_request *areq, struct meson_
}
}
+static void reverse_keyiv(u32 *keyiv, u32 *iv)
+{
+ int size = AES_BLOCK_SIZE / sizeof(u32);
+ int i;
+
+ for (i = 0; i < size; i++)
+ *(keyiv + size - i - 1) = cpu_to_be32(*(iv + i));
+}
+
static void meson_setup_keyiv_descs(struct cipher_ctx *ctx)
{
struct meson_cipher_req_ctx *rctx = skcipher_request_ctx(ctx->areq);
@@ -154,8 +163,12 @@ static void meson_setup_keyiv_descs(struct cipher_ctx *ctx)
if (ctx->tloffset)
return;
- if (blockmode == DESC_OPMODE_CBC) {
- memcpy(op->keyiv + AES_MAX_KEY_SIZE, ctx->areq->iv, ivsize);
+ if (blockmode == DESC_OPMODE_CBC || blockmode == DESC_OPMODE_CTR) {
+ if (blockmode == DESC_OPMODE_CTR && mc->pdata->reverse_keyiv)
+ reverse_keyiv((u32 *)(op->keyiv + AES_MAX_KEY_SIZE), (u32 *)ctx->areq->iv);
+ else
+ memcpy(op->keyiv + AES_MAX_KEY_SIZE, ctx->areq->iv, ivsize);
+
dma_sync_single_for_device(mc->dev, ctx->keyiv.addr,
ctx->keyiv.len, DMA_TO_DEVICE);
}
@@ -186,6 +199,7 @@ static bool meson_setup_data_descs(struct cipher_ctx *ctx)
struct meson_desc *desc = &mc->chanlist[rctx->flow].tl[ctx->tloffset];
unsigned int blocksize = crypto_skcipher_blocksize(tfm);
unsigned int blockmode = algt->blockmode;
+ unsigned int ivsize = crypto_skcipher_ivsize(tfm);
unsigned int maxlen = rounddown(DESC_MAXLEN, blocksize);
unsigned int todo;
u32 v;
@@ -204,8 +218,15 @@ static bool meson_setup_data_descs(struct cipher_ctx *ctx)
ctx->src_offset += todo;
ctx->dst_offset += todo;
+ if (blockmode == DESC_OPMODE_CTR) {
+ unsigned int nblocks = todo / blocksize;
+
+ while (nblocks--)
+ crypto_inc(ctx->areq->iv, ivsize);
+ }
+
v = DESC_OWN | blockmode | op->keymode | todo;
- if (rctx->op_dir == MESON_ENCRYPT)
+ if (rctx->op_dir == MESON_ENCRYPT || blockmode == DESC_OPMODE_CTR)
v |= DESC_ENCRYPTION;
if (!ctx->cryptlen || ctx->tloffset == MAXDESC)
@@ -322,7 +343,8 @@ static int meson_cipher(struct skcipher_request *areq)
if (ctx.keyiv.len == AES_KEYSIZE_192)
ctx.keyiv.len = AES_MAX_KEY_SIZE;
- if (algt->blockmode == DESC_OPMODE_CBC) {
+ if (algt->blockmode == DESC_OPMODE_CBC ||
+ algt->blockmode == DESC_OPMODE_CTR) {
memcpy(op->keyiv + AES_MAX_KEY_SIZE, areq->iv, ivsize);
ctx.keyiv.len = AES_MAX_KEY_SIZE + ivsize;
}
@@ -535,6 +557,35 @@ static struct meson_alg_template algs[] = {
.do_one_request = meson_handle_cipher_request,
},
},
+{
+ .type = CRYPTO_ALG_TYPE_SKCIPHER,
+ .blockmode = DESC_OPMODE_CTR,
+ .alg.skcipher.base = {
+ .base = {
+ .cra_name = "ctr(aes)",
+ .cra_driver_name = "ctr-aes-gxl",
+ .cra_priority = 400,
+ .cra_blocksize = AES_BLOCK_SIZE,
+ .cra_flags = CRYPTO_ALG_TYPE_SKCIPHER |
+ CRYPTO_ALG_ASYNC | CRYPTO_ALG_ALLOCATES_MEMORY |
+ CRYPTO_ALG_NEED_FALLBACK,
+ .cra_ctxsize = sizeof(struct meson_cipher_tfm_ctx),
+ .cra_module = THIS_MODULE,
+ .cra_alignmask = 0xf,
+ .cra_init = meson_cipher_init,
+ .cra_exit = meson_cipher_exit,
+ },
+ .min_keysize = AES_MIN_KEY_SIZE,
+ .max_keysize = AES_MAX_KEY_SIZE,
+ .ivsize = AES_BLOCK_SIZE,
+ .setkey = meson_aes_setkey,
+ .encrypt = meson_skencrypt,
+ .decrypt = meson_skdecrypt,
+ },
+ .alg.skcipher.op = {
+ .do_one_request = meson_handle_cipher_request,
+ },
+},
};
int meson_cipher_register(struct meson_dev *mc)
diff --git a/drivers/crypto/amlogic/amlogic-gxl-core.c b/drivers/crypto/amlogic/amlogic-gxl-core.c
index c5ee40196801..c3cec58cf443 100644
--- a/drivers/crypto/amlogic/amlogic-gxl-core.c
+++ b/drivers/crypto/amlogic/amlogic-gxl-core.c
@@ -290,6 +290,7 @@ static const struct meson_pdata meson_gxl_pdata = {
.status_reg = 0x4,
.setup_desc_cnt = 3,
.hasher_supported = false,
+ .reverse_keyiv = true,
};
static const struct of_device_id meson_crypto_of_match_table[] = {
diff --git a/drivers/crypto/amlogic/amlogic-gxl.h b/drivers/crypto/amlogic/amlogic-gxl.h
index cebdfd81f6e2..de11e174f03d 100644
--- a/drivers/crypto/amlogic/amlogic-gxl.h
+++ b/drivers/crypto/amlogic/amlogic-gxl.h
@@ -24,6 +24,7 @@
#define DESC_OPMODE_ECB (0 << 26)
#define DESC_OPMODE_CBC (1 << 26)
+#define DESC_OPMODE_CTR (2 << 26)
#define DESC_OPMODE_SHA (0 << 26)
#define DESC_MAXLEN GENMASK(16, 0)
@@ -103,6 +104,7 @@ struct meson_pdata {
u32 status_reg;
u32 setup_desc_cnt;
bool hasher_supported;
+ bool reverse_keyiv;
};
/*
--
2.34.1
Powered by blists - more mailing lists