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Date: Tue,  5 Mar 2024 14:53:35 +0000
From: "levi.yun" <yeoreum.yun@....com>
To: catalin.marinas@....com,
	will@...nel.org,
	mark.rutland@....com,
	peterz@...radead.org,
	mathieu.desnoyers@...icios.com
Cc: linux-arm-kernel@...ts.infradead.org,
	linux-kernel@...r.kernel.org,
	nd@....com,
	"levi.yun" <yeoreum.yun@....com>,
	stable@...r.kernel.org,
	Aaron Lu <aaron.lu@...el.com>
Subject: [PATCH] arm64/mm: Add memory barrier for mm_cid

Currently arm64's switch_mm() doesn't always have an smp_mb()
which the core scheduler code has depended upon since commit:

    commit 223baf9d17f25 ("sched: Fix performance regression introduced by mm_cid")

If switch_mm() doesn't call smp_mb(), sched_mm_cid_remote_clear()
can unset the activly used cid when it fails to observe active task after it
sets lazy_put.

By adding an smp_mb() in arm64's check_and_switch_context(),
Guarantee to observe active task after sched_mm_cid_remote_clear()
success to set lazy_put.

Signed-off-by: levi.yun <yeoreum.yun@....com>
Fixes: 223baf9d17f2 ("sched: Fix performance regression introduced by mm_cid")
Cc: <stable@...r.kernel.org> # 6.4.x
Cc: Mathieu Desnoyers <mathieu.desnoyers@...icios.com>
Cc: Catalin Marinas <catalin.marinas@....com>
Cc: Mark Rutland <mark.rutland@....com>
Cc: Will Deacon <will@...nel.org>
Cc: Peter Zijlstra <peterz@...radead.org>
Cc: Aaron Lu <aaron.lu@...el.com>
---
 I'm really sorry if you got this multiple times.
 I had some problems with the SMTP server...

 arch/arm64/mm/context.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c
index 188197590fc9..7a9e8e6647a0 100644
--- a/arch/arm64/mm/context.c
+++ b/arch/arm64/mm/context.c
@@ -268,6 +268,11 @@ void check_and_switch_context(struct mm_struct *mm)
 	 */
 	if (!system_uses_ttbr0_pan())
 		cpu_switch_mm(mm->pgd, mm);
+
+	/*
+	 * See the comments on switch_mm_cid describing user -> user transition.
+	 */
+	smp_mb();
 }

 unsigned long arm64_mm_context_get(struct mm_struct *mm)
--
LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7}


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