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Message-ID: <55a6df07d26849e89c839f80ca5996b9@AcuMS.aculab.com>
Date: Tue, 5 Mar 2024 09:27:22 +0000
From: David Laight <David.Laight@...LAB.COM>
To: 'Arnd Bergmann' <arnd@...db.de>, Christophe Leroy
<christophe.leroy@...roup.eu>, Guenter Roeck <linux@...ck-us.net>, "Russell
King" <linux@...linux.org.uk>
CC: "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>, "Palmer
Dabbelt" <palmer@...belt.com>, Charlie Jenkins <charlie@...osinc.com>, "James
E . J . Bottomley" <James.Bottomley@...senpartnership.com>, Helge Deller
<deller@....de>, Palmer Dabbelt <palmer@...osinc.com>, Geert Uytterhoeven
<geert@...ux-m68k.org>, Andrew Morton <akpm@...ux-foundation.org>, "Parisc
List" <linux-parisc@...r.kernel.org>, Linux ARM
<linux-arm-kernel@...ts.infradead.org>
Subject: RE: [PATCH v11] lib: checksum: Use aligned accesses for ip_fast_csum
and csum_ipv6_magic tests
From: Arnd Bergmann
> Sent: 04 March 2024 13:40
...
> > If not, then the test has to be fixed to only use word-aligned IPv6
> > addresses.
>
> Because of the gcc issue I mentioned, net/ipv6/ip6_checksum.c
> and anything else that accesses misaligned ipv6 headers may need
> to be changed as well. Marking in6_addr as '__packed __aligned(2)'
> should be sufficient for that. This will prevent gcc from issuing
> ldm or ldrd on ARMv6+ as well as making optimization based on
> the two lower bits of the address being zero on x86 and others.
Eh? x86 pretty much doesn't care unless you are using AVX.
> The downside is that it forces 16-bit loads and stores to be
> used on architectures that don't have efficient unaligned
> access (armv5, alpha, mips, sparc and xtensa among others)
> even when the IP headers are fully aligned.
Aren't the later accesses to the header also going to fault?
IIRC there is an skb_pull() call to ensure all the IP header
is in the linear skb fragment?
Perhaps there should be an skb_pull_aligned() that will ensure
the data is 32bit aligned on systems where the misaligned accesses
fault?
There might still need to be something to stop gcc generating
ldm/ldrd which can fault on systems where a normal register
read wouldn't.
Do any recent arm cpu have the strongarm 'feature' than ldm
always took 16 clocks?
David
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