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Message-ID:
<SH0PR01MB08411D27D7A3CD39CDDE618FF921A@SH0PR01MB0841.CHNPR01.prod.partner.outlook.cn>
Date: Wed, 6 Mar 2024 16:06:11 +0000
From: Joshua Yeong <joshua.yeong@...rfivetech.com>
To: Frank Li <Frank.Li@....com>
CC: "alexandre.belloni@...tlin.com" <alexandre.belloni@...tlin.com>,
"conor.culhane@...vaco.com" <conor.culhane@...vaco.com>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"gregkh@...uxfoundation.org" <gregkh@...uxfoundation.org>,
"ilpo.jarvinen@...ux.intel.com" <ilpo.jarvinen@...ux.intel.com>,
"imx@...ts.linux.dev" <imx@...ts.linux.dev>, "jirislaby@...nel.org"
<jirislaby@...nel.org>, "joe@...ches.com" <joe@...ches.com>,
"krzysztof.kozlowski+dt@...aro.org" <krzysztof.kozlowski+dt@...aro.org>,
"krzysztof.kozlowski@...aro.org" <krzysztof.kozlowski@...aro.org>,
"linux-i3c@...ts.infradead.org" <linux-i3c@...ts.infradead.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"linux-serial@...r.kernel.org" <linux-serial@...r.kernel.org>,
"miquel.raynal@...tlin.com" <miquel.raynal@...tlin.com>, "robh@...nel.org"
<robh@...nel.org>, "zbigniew.lukwinski@...ux.intel.com"
<zbigniew.lukwinski@...ux.intel.com>
Subject: RE: [PATCH v8 5/8] i3c: target: add svc target controller support
Hi Frank,
Apologize I replied to the older patch series version. I copy the text from there to here instead.
> -----Original Message-----
> From: linux-i3c <linux-i3c-bounces@...ts.infradead.org> On Behalf Of Frank Li
> Sent: Friday, February 9, 2024 1:01 AM
> To: frank.li@....com
> Cc: alexandre.belloni@...tlin.com; conor.culhane@...vaco.com;
> devicetree@...r.kernel.org; gregkh@...uxfoundation.org;
> ilpo.jarvinen@...ux.intel.com; imx@...ts.linux.dev; jirislaby@...nel.org;
> joe@...ches.com; krzysztof.kozlowski+dt@...aro.org;
> krzysztof.kozlowski@...aro.org; linux-i3c@...ts.infradead.org; linux-
> kernel@...r.kernel.org; linux-serial@...r.kernel.org;
> miquel.raynal@...tlin.com; robh@...nel.org;
> zbigniew.lukwinski@...ux.intel.com
> Subject: [PATCH v8 5/8] i3c: target: add svc target controller support
>
> Add Silvaco I3C target controller support
>
> Signed-off-by: Frank Li <Frank.Li@....com>
> ---
>
> Notes:
> Chagne from v7 to v8
> -reorder header files
> - add missed header files
>
> Change from v3 to v7
> - none
> Change from v2 to v3
> - fix build warning
>
> drivers/i3c/master/Makefile | 2 +-
> drivers/i3c/master/svc-i3c-main.c | 35 +-
> drivers/i3c/master/svc-i3c-target.c | 776
I think putting target mode files under "master" might not make sense.
We might have to consider that we may have a "secondary master" mode.
Some other ways of splitting or handling of target mode is needed here.
>
> static const struct dev_pm_ops svc_i3c_pm_ops = { diff --git
> a/drivers/i3c/master/svc-i3c-target.c b/drivers/i3c/master/svc-i3c-targetc
> new file mode 100644
> index 0000000000000..06210ed0c3219
> --- /dev/null
> +++ b/drivers/i3c/master/svc-i3c-target.c
> @@ -0,0 +1,776 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright 2023 NXP.
> + *
> + * Author: Frank Li <Frank.Li@....com>
> + */
> +
> +#include <linux/bits.h>
> +#include <linux/bitfield.h>
> +#include <linux/clk.h>
> +#include <linux/completion.h>
> +#include <linux/errno.h>
> +#include <linux/i3c/device.h>
> +#include <linux/i3c/target.h>
> +#include <linux/interrupt.h>
> +#include <linux/iopoll.h>
> +#include <linux/kernel.h>
> +#include <linux/list.h>
> +#include <linux/module.h>
> +#include <linux/mod_devicetable.h>
> +#include <linux/of.h>
> +#include <linux/pinctrl/consumer.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/spinlock.h>
> +#include <linux/workqueue.h>
> +
> +#include "svc-i3c.h"
> +
> +enum i3c_clks {
> + PCLK,
> + FCLK,
> + SCLK,
> + MAXCLK,
> +};
> +
> +struct svc_i3c_target {
> + struct device *dev;
> + void __iomem *regs;
> + int irq;
> + struct clk_bulk_data clks[MAXCLK];
> +
> + struct list_head txq;
> + spinlock_t txq_lock; /* protect tx queue */
> + struct list_head rxq;
> + spinlock_t rxq_lock; /* protect rx queue */
> + struct list_head cq;
> + spinlock_t cq_lock; /* protect complete queue */
> +
> + struct work_struct work;
> + struct workqueue_struct *workqueue;
> +
> + struct completion dacomplete;
> + struct i3c_target_ctrl_features features;
> +
> + spinlock_t ctrl_lock; /* protext access SCTRL register */ };
> +
> +#define I3C_SCONFIG 0x4
> +#define I3C_SCONFIG_SLVENA_MASK BIT(0)
> +#define I3C_SCONFIG_OFFLINE_MASK BIT(9)
> +#define I3C_SCONFIG_SADDR_MASK GENMASK(31, 25)
> +
> +#define I3C_SSTATUS 0x8
> +#define I3C_SSTATUS_STNOTSTOP_MASK BIT(0)
> +#define I3C_SSTATUS_STOP_MASK BIT(10)
> +#define I3C_SSTATUS_RX_PEND_MASK BIT(11)
> +#define I3C_SSTATUS_TXNOTFULL_MASK BIT(12)
> +#define I3C_SSTATUS_DACHG_MASK BIT(13)
> +#define I3C_SSTATUS_EVDET_MASK GENMASK(21, 20)
> +#define I3C_SSTATUS_EVDET_ACKED 0x3
> +#define I3C_SSTATUS_IBIDIS_MASK BIT(24)
> +#define I3C_SSTATUS_HJDIS_MASK BIT(27)
> +
> +#define I3C_SCTRL 0xc
> +#define I3C_SCTRL_EVENT_MASK GENMASK(1, 0)
> +#define I3C_SCTRL_EVENT_IBI 0x1
> +#define I3C_SCTRL_EVENT_HOTJOIN 0x3
> +#define I3C_SCTRL_EXTDATA_MASK BIT(3)
> +#define I3C_SCTRL_IBIDATA_MASK GENMASK(15, 8)
> +
> +#define I3C_SINTSET 0x10
> +#define I3C_SINTCLR 0x14
> +#define I3C_SINT_START BIT(8)
> +#define I3C_SINT_MATCHED BIT(9)
> +#define I3C_SINT_STOP BIT(10)
> +#define I3C_SINT_RXPEND BIT(11)
> +#define I3C_SINT_TXSEND BIT(12)
> +#define I3C_SINT_DACHG BIT(13)
> +#define I3C_SINT_CCC BIT(14)
> +#define I3C_SINT_ERRWARN BIT(15)
> +#define I3C_SINT_DDRMAATCHED BIT(16)
> +#define I3C_SINT_CHANDLED BIT(17)
> +#define I3C_SINT_EVENT BIT(18)
> +#define I3C_SINT_SLVRST BIT(19)
> +
> +#define I3C_SDATACTRL 0x2c
> +#define I3C_SDATACTRL_RXEMPTY_MASK BIT(31)
> +#define I3C_SDATACTRL_TXFULL_MASK BIT(30)
> +#define I3C_SDATACTRL_RXCOUNT_MASK GENMASK(28, 24)
> +#define I3C_SDATACTRL_TXCOUNT_MASK GENMASK(20, 16)
> +#define I3C_SDATACTRL_FLUSHFB_MASK BIT(1)
> +#define I3C_SDATACTRL_FLUSHTB_MASK BIT(0)
> +
> +#define I3C_SWDATAB 0x30
> +#define I3C_SWDATAB_END_ALSO_MASK BIT(16)
> +#define I3C_SWDATAB_END_MASK BIT(8)
> +
> +#define I3C_SWDATAE 0x34
> +#define I3C_SRDATAB 0x40
> +
> +#define I3C_SCAPABILITIES 0x60
> +#define I3C_SCAPABILITIES_FIFOTX_MASK GENMASK(27, 26)
> +#define I3C_SCAPABILITIES_FIFORX_MASK GENMASK(29, 28)
> +
> +#define I3C_SMAXLIMITS 0x68
> +#define I3C_SMAXLIMITS_MAXRD_MASK GENMASK(11, 0)
> +#define I3C_SMAXLIMITS_MAXWR_MASK GENMASK(27, 16)
> +
> +#define I3C_SIDPARTNO 0x6c
> +
> +#define I3C_SIDEXT 0x70
> +#define I3C_SIDEXT_BCR_MASK GENMASK(23, 16)
> +#define I3C_SIDEXT_DCR_MASK GENMASK(15, 8)
> +#define I3C_SVENDORID 0x74
> +
> +#define I3C_SMAPCTRL0 0x11c
> +#define I3C_SMAPCTRL0_ENA_MASK BIT(0)
> +#define I3C_SMAPCTRL0_DA_MASK GENMASK(7, 1)
> +
> +#define I3C_IBIEXT1 0x140
> +#define I3C_IBIEXT1_CNT_MASK GEN_MASK(2, 0)
> +#define I3C_IBIEXT1_MAX_MASK GEN_MASK(4, 6)
> +#define I3C_IBIEXT1_EXT1_SHIFT 8
> +#define I3C_IBIEXT1_EXT2_SHIFT 16
> +#define I3C_IBIEXT1_EXT3_SHIFT 24
> +
> +#define I3C_IBIEXT2 0x144
> +#define I3C_IBIEXT2_EXT4_SHIFT 0
> +#define I3C_IBIEXT2_EXT5_SHIFT 8
> +#define I3C_IBIEXT2_EXT6_SHIFT 16
> +#define I3C_IBIEXT2_EXT7_SHIFT 24
> +
There is couple of space formatting here that requires to be fixed.
Cheers,
Joshua
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