linux-kernel - samsung: clk: re-parent MUX to OSCCLK at run-time

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Message-ID: <d508dfc1-bc28-4470-92aa-cf71915966f4@linaro.org>
Date: Wed, 6 Mar 2024 03:20:05 +0000
From: Tudor Ambarus <tudor.ambarus@...aro.org>
To: Sylwester Nawrocki <s.nawrocki@...sung.com>,
 Chanwoo Choi <cw00.choi@...sung.com>, Alim Akhtar <alim.akhtar@...sung.com>
Cc: Sam Protsenko <semen.protsenko@...aro.org>,
 Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
 linux-samsung-soc@...r.kernel.org, linux-clk@...r.kernel.org,
 "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
 linux-arm-kernel <linux-arm-kernel@...ts.infradead.org>,
 Peter Griffin <peter.griffin@...aro.org>,
 André Draszik <andre.draszik@...aro.org>,
 William McVicker <willmcvicker@...gle.com>, kernel-team@...roid.com
Subject: samsung: clk: re-parent MUX to OSCCLK at run-time

Hi,

Trying to get some feedback from the samsung experts. Please consider
the following:

                         ---------------------------------------------
                        |                                CMU_PERIC0   |
                        |                                             |
                        |  MUX_USI                                    |
                        |                                             |
                        |  |\                                         |
              OSCCLK ---|->| \                                        |
                        |  |  \                                       |
                        |  | M |                                      |
                        |  | U |--> DIV_CLK_PERIC0_USI*_ --> GATE_USI |
                        |  | X |        (1 ~ 16)                      |
                        |  |  /                                       |
DIV_CLKCMU_PERIC0_IP ---|->| /                                        |
    (1 ~ 16)          | |  |/                                         |
                      | |                                             |
                      | |                                             |
                      | |  MUX_I3C                                    |
                      | |                                             |
                      | |  |\                                         |
                      --|->| \                                        |
                        |  |  \                                       |
                        |  | M |                                      |
                        |  | U |--> DIV_CLK_PERIC0_I3C --> GATE_I3C   |
                        |  | X |                                      |
                        |  |  /                                       |
              OSCCLK ---|->| /                                        |
                        |  |/                                         |
                        |                                             |
                         ---------------------------------------------

Is it fine to re-parent the MUX_USI from above to OSCCLK at run-time,
during normal operation mode? Experimentally I determined that it's
fine, but the datasheet that I'm reading mentions OSCCLK just in the
low-power mode context:
i/ CMU ... "Communicates with Power Management Unit (PMU) to stop clocks
or switch OSC clock before entering a Low-Power mode to reduce power
consumption by minimizing clock toggling".
ii/ "All CMUs have MUXs to change the OSCCLK during power-down mode".

Re-parenting the MUX to OSCCLK allows lower clock rates for the USI
blocks than the DIV_CLK_PERIC0_USI can offer. For a USI clock rate below
6.25 MHz I have to either reparent MUX_USI to OSCCLK, or to propagate
the clock rate to the common divider DIV_CLKCMU_PERIC0_IP. I find the
propagation to the common DIV less desirable as a low USI clock rate
affects I3C by lowering its clock rate too. Worse, if the common bus
divider is not protected (using CLK_SET_RATE_GATE), USI can lower the
I3C clock rate without I3C noticing.

Either re-parenting the MUX_USI to OSCCLK, or propagating the clock rate
to DIV_CLKCMU_PERIC0_IP allows the same clock ranges. The first with the
benefit of not affecting the clock rate of I3C for USI clock rates below
6.25 MHz. Is it fine to re-parent MUX_USI to OSCCLK at run-time?

If no feedback is received I lean towards propagating the USI clock rate
to the common divider, but by protecting it with CLK_SET_RATE_GATE.

Feel free to add in To: or Cc: whoever might be interested. Thanks,
ta