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Message-ID: <CA+V-a8tX8F=hhEBTUE2o1Ds=r8duZGWt3i4ottTC6vjsMm2PCw@mail.gmail.com>
Date: Wed, 6 Mar 2024 09:15:38 +0000
From: "Lad, Prabhakar" <prabhakar.csengg@...il.com>
To: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
Cc: Geert Uytterhoeven <geert+renesas@...der.be>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>, Jiri Slaby <jirislaby@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>, Conor Dooley <conor+dt@...nel.org>,
Magnus Damm <magnus.damm@...il.com>, linux-kernel@...r.kernel.org,
linux-serial@...r.kernel.org, devicetree@...r.kernel.org,
linux-renesas-soc@...r.kernel.org,
Fabrizio Castro <fabrizio.castro.jz@...esas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: Re: [PATCH] dt-bindings: serial: renesas,scif: Document R9A09G057 support
Hi Krzysztof,
Thank you for the review.
On Wed, Mar 6, 2024 at 7:34 AM Krzysztof Kozlowski
<krzysztof.kozlowski@...aro.org> wrote:
>
> On 05/03/2024 18:16, Prabhakar wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> >
> > Document support for the Serial Communication Interface with FIFO (SCIF)
> > available in the Renesas RZ/V2H(P) (R9A09G057) SoC. The SCIF interface in
> > the Renesas RZ/V2H(P) is similar to that available in the RZ/G2L
> > (R9A07G044) SoC, with the only difference being that the RZ/V2H(P) SoC has
> > three additional interrupts: one for Tx end/Rx ready and the other two for
> > Rx and Tx buffer full, which are edge-triggered.
> >
> > No driver changes are required as generic compatible string
> > "renesas,scif-r9a07g044" will be used as a fallback on RZ/V2H(P) SoC.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> > Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@...esas.com>
> > ---
> > .../bindings/serial/renesas,scif.yaml | 21 +++++++++++++++++++
> > 1 file changed, 21 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/serial/renesas,scif.yaml b/Documentation/devicetree/bindings/serial/renesas,scif.yaml
> > index 4610a5bd580c..b2c2305e352c 100644
> > --- a/Documentation/devicetree/bindings/serial/renesas,scif.yaml
> > +++ b/Documentation/devicetree/bindings/serial/renesas,scif.yaml
> > @@ -80,6 +80,7 @@ properties:
> > - renesas,scif-r9a07g043 # RZ/G2UL and RZ/Five
> > - renesas,scif-r9a07g054 # RZ/V2L
> > - renesas,scif-r9a08g045 # RZ/G3S
> > + - renesas,scif-r9a09g057 # RZ/V2H(P)
> > - const: renesas,scif-r9a07g044 # RZ/G2{L,LC} fallback
> >
> > reg:
> > @@ -101,6 +102,16 @@ properties:
> > - description: Break interrupt
> > - description: Data Ready interrupt
> > - description: Transmit End interrupt
> > + - items:
> > + - description: Error interrupt
> > + - description: Receive buffer full interrupt
> > + - description: Transmit buffer empty interrupt
> > + - description: Break interrupt
> > + - description: Data Ready interrupt
> > + - description: Transmit End interrupt
> > + - description: Transmit End/Data Ready interrupt
> > + - description: Receive buffer full interrupt (EDGE trigger)
> > + - description: Transmit buffer empty interrupt (EDGE trigger)
>
> You should narrow the choice per variant. Your patch is now saying that
> all devices could have 9 interrupts.
>
Ok I will fix the existing binding first and then add support for RZ/V2H SoC.
Cheers,
Prabhakar
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