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Message-Id: <20240306101625.795732-8-alexander.stein@ew.tq-group.com>
Date: Wed, 6 Mar 2024 11:16:24 +0100
From: Alexander Stein <alexander.stein@...tq-group.com>
To: Andrzej Hajda <andrzej.hajda@...el.com>,
Neil Armstrong <neil.armstrong@...aro.org>,
Robert Foss <rfoss@...nel.org>,
Laurent Pinchart <Laurent.pinchart@...asonboard.com>,
Jonas Karlman <jonas@...boo.se>,
Jernej Skrabec <jernej.skrabec@...il.com>,
David Airlie <airlied@...il.com>,
Daniel Vetter <daniel@...ll.ch>,
Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>,
Maxime Ripard <mripard@...nel.org>,
Thomas Zimmermann <tzimmermann@...e.de>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>,
Vinod Koul <vkoul@...nel.org>,
Kishon Vijay Abraham I <kishon@...nel.org>,
Shawn Guo <shawnguo@...nel.org>,
Sascha Hauer <s.hauer@...gutronix.de>,
Pengutronix Kernel Team <kernel@...gutronix.de>,
Fabio Estevam <festevam@...il.com>,
Sandor Yu <Sandor.yu@....com>
Cc: Alexander Stein <alexander.stein@...tq-group.com>,
dri-devel@...ts.freedesktop.org,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
linux-phy@...ts.infradead.org,
imx@...ts.linux.dev,
linux-arm-kernel@...ts.infradead.org,
linux@...tq-group.com
Subject: [PATCH v15 7/8] arm64: dts: imx8mq: Add DCSS + HDMI/DP display pipeline
This adds DCSS + MHDP + MHDP PHY nodes. PHY mode (DP/HDMI) is selected
by the connector type connected to mhdp port@1 endpoint.
Signed-off-by: Alexander Stein <alexander.stein@...tq-group.com>
---
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 68 +++++++++++++++++++++++
1 file changed, 68 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index c6dc3ba0d43b2..76fc3fd56fbf7 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -1595,6 +1595,74 @@ aips4: bus@...00000 { /* AIPS4 */
#size-cells = <1>;
ranges = <0x32c00000 0x32c00000 0x400000>;
+ mdhp_phy: phy@...00000 {
+ compatible = "fsl,imx8mq-hdptx-phy";
+ reg = <0x32c00000 0x100000>;
+ #phy-cells = <0>;
+ clocks = <&hdmi_phy_27m>, <&clk IMX8MQ_CLK_DISP_APB_ROOT>;
+ clock-names = "ref", "apb";
+ };
+
+ mhdp: bridge@...00000 {
+ compatible = "fsl,imx8mq-mhdp8501";
+ reg = <0x32c00000 0x100000>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "plug_in", "plug_out";
+ clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>;
+ phys = <&mdhp_phy>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mhdp_in: endpoint {
+ remote-endpoint = <&dcss_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ mhdp_out: endpoint {
+ };
+ };
+ };
+ };
+
+ dcss: display-controller@...00000 {
+ compatible = "nxp,imx8mq-dcss";
+ reg = <0x32e00000 0x2d000>, <0x32e2f000 0x1000>;
+ interrupt-parent = <&irqsteer>;
+ interrupts = <6>, <8>, <9>;
+ interrupt-names = "ctxld", "ctxld_kick", "vblank";
+ clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>,
+ <&clk IMX8MQ_CLK_DISP_AXI_ROOT>,
+ <&clk IMX8MQ_CLK_DISP_RTRM_ROOT>,
+ <&clk IMX8MQ_VIDEO2_PLL_OUT>,
+ <&clk IMX8MQ_CLK_DISP_DTRC>;
+ clock-names = "apb", "axi", "rtrm", "pix", "dtrc";
+ assigned-clocks = <&clk IMX8MQ_CLK_DISP_AXI>,
+ <&clk IMX8MQ_CLK_DISP_RTRM>,
+ <&clk IMX8MQ_VIDEO2_PLL1_REF_SEL>;
+ assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>,
+ <&clk IMX8MQ_SYS1_PLL_800M>,
+ <&clk IMX8MQ_CLK_27M>;
+ assigned-clock-rates = <800000000>,
+ <400000000>;
+ status = "disabled";
+
+ port {
+ dcss_out: endpoint {
+ remote-endpoint = <&mhdp_in>;
+ };
+ };
+ };
+
irqsteer: interrupt-controller@...2d000 {
compatible = "fsl,imx8m-irqsteer", "fsl,imx-irqsteer";
reg = <0x32e2d000 0x1000>;
--
2.34.1
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