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Message-ID: <CAA8EJprc_xjejMANBjDkA2_FnRcYSJYsmM4VOvsKu1FkuMvGeg@mail.gmail.com>
Date: Wed, 6 Mar 2024 16:38:41 +0200
From: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
To: Chukun Pan <amadeus@....edu.cn>
Cc: Bjorn Andersson <andersson@...nel.org>, Konrad Dybcio <konrad.dybcio@...aro.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>, Conor Dooley <conor+dt@...nel.org>,
Rob Herring <robh@...nel.org>, linux-arm-msm@...r.kernel.org,
linux-kernel@...r.kernel.org, devicetree@...r.kernel.org
Subject: Re: [PATCH v2 3/4] arm64: dts: qcom: ipq6018: move mp5496 regulator
outside soc dtsi
On Wed, 6 Mar 2024 at 16:04, Chukun Pan <amadeus@....edu.cn> wrote:
>
> Some IPQ60xx SoCs don't have the mp5496 pmic chips. The mp5496
> pmic is not part of the ipq60xx SoC, and the mp5496 node is
> the same for devices with pmic, so create a common dtsi.
Please inline this dtsi file into the board file. While it might seem
to make life easier, having such includes makes following regulator
settings much harder. Especially once a board or two start overriding
or expanding those settings.
>
> Signed-off-by: Chukun Pan <amadeus@....edu.cn>
> ---
> arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 1 +
> arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi | 29 ++++++++++++++++++++
> arch/arm64/boot/dts/qcom/ipq6018.dtsi | 14 ----------
> 3 files changed, 30 insertions(+), 14 deletions(-)
> create mode 100644 arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi
>
> diff --git a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
> index f5f4827c0e17..8331890e529e 100644
> --- a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
> +++ b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
> @@ -8,6 +8,7 @@
> /dts-v1/;
>
> #include "ipq6018.dtsi"
> +#include "ipq6018-mp5496.dtsi"
>
> / {
> model = "Qualcomm Technologies, Inc. IPQ6018/AP-CP01-C1";
> diff --git a/arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi b/arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi
> new file mode 100644
> index 000000000000..841fd757bee7
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/ipq6018-mp5496.dtsi
> @@ -0,0 +1,29 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +
> +&rpm_requests {
> + regulators {
> + compatible = "qcom,rpm-mp5496-regulators";
> +
> + ipq6018_s2: s2 {
> + regulator-min-microvolt = <725000>;
> + regulator-max-microvolt = <1062500>;
> + regulator-always-on;
> + };
> + };
> +};
> +
> +&CPU0 {
> + cpu-supply = <&ipq6018_s2>;
> +};
> +
> +&CPU1 {
> + cpu-supply = <&ipq6018_s2>;
> +};
> +
> +&CPU2 {
> + cpu-supply = <&ipq6018_s2>;
> +};
> +
> +&CPU3 {
> + cpu-supply = <&ipq6018_s2>;
> +};
> diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> index 064b5706a289..823b87fdcefd 100644
> --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> @@ -43,7 +43,6 @@ CPU0: cpu@0 {
> clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
> clock-names = "cpu";
> operating-points-v2 = <&cpu_opp_table>;
> - cpu-supply = <&ipq6018_s2>;
> #cooling-cells = <2>;
> };
>
> @@ -56,7 +55,6 @@ CPU1: cpu@1 {
> clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
> clock-names = "cpu";
> operating-points-v2 = <&cpu_opp_table>;
> - cpu-supply = <&ipq6018_s2>;
> #cooling-cells = <2>;
> };
>
> @@ -69,7 +67,6 @@ CPU2: cpu@2 {
> clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
> clock-names = "cpu";
> operating-points-v2 = <&cpu_opp_table>;
> - cpu-supply = <&ipq6018_s2>;
> #cooling-cells = <2>;
> };
>
> @@ -82,7 +79,6 @@ CPU3: cpu@3 {
> clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
> clock-names = "cpu";
> operating-points-v2 = <&cpu_opp_table>;
> - cpu-supply = <&ipq6018_s2>;
> #cooling-cells = <2>;
> };
>
> @@ -184,16 +180,6 @@ glink-edge {
> rpm_requests: rpm-requests {
> compatible = "qcom,rpm-ipq6018";
> qcom,glink-channels = "rpm_requests";
> -
> - regulators {
> - compatible = "qcom,rpm-mp5496-regulators";
> -
> - ipq6018_s2: s2 {
> - regulator-min-microvolt = <725000>;
> - regulator-max-microvolt = <1062500>;
> - regulator-always-on;
> - };
> - };
> };
> };
> };
> --
> 2.25.1
>
>
--
With best wishes
Dmitry
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