linux-kernel - Re: [PATCH net-next v3 06/12] net: ethernet: oa_tc6: implement internal PHY initialization

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Date: Thu, 7 Mar 2024 02:13:24 +0100
From: Andrew Lunn <andrew@...n.ch>
To: Parthiban Veerasooran <Parthiban.Veerasooran@...rochip.com>
Cc: davem@...emloft.net, edumazet@...gle.com, kuba@...nel.org,
	pabeni@...hat.com, horms@...nel.org, saeedm@...dia.com,
	anthony.l.nguyen@...el.com, netdev@...r.kernel.org,
	linux-kernel@...r.kernel.org, corbet@....net,
	linux-doc@...r.kernel.org, robh+dt@...nel.org,
	krzysztof.kozlowski+dt@...aro.org, conor+dt@...nel.org,
	devicetree@...r.kernel.org, horatiu.vultur@...rochip.com,
	ruanjinjie@...wei.com, steen.hegelund@...rochip.com,
	vladimir.oltean@....com, UNGLinuxDriver@...rochip.com,
	Thorsten.Kummermehr@...rochip.com, Pier.Beruto@...emi.com,
	Selvamani.Rajagopal@...emi.com, Nicolas.Ferre@...rochip.com,
	benjamin.bigler@...nformulastudent.ch
Subject: Re: [PATCH net-next v3 06/12] net: ethernet: oa_tc6: implement
 internal PHY initialization

> +/* PHY Clause 22 and 29 registers base address and mask */
> +#define OA_TC6_PHY_STD_REG_ADDR_BASE		0xFF00
> +#define OA_TC6_PHY_STD_REG_ADDR_MASK		0x3F

[Goes and looks a 802.3]

Clause 29 is "System considerations for multisegment 100BASE-T networks"

I don't see any mention of registers in there.

TC6 says:

"Clause 22 standard registers and Clause 22 extended registers (Clause
29) are directly mapped into MMS 0 as shown in Table 7."

Going back to 802.3, we have 22.2.4:

The MII basic register set consists of two registers referred to as
the Control register (Register 0) and the Status register (Register
1). All PHYs that provide an MII Management Interface shall
incorporate the basic register set. All PHYs that provide a GMII shall
incorporate an extended basic register set consisting of the Control
register (Register 0), Status register (Register 1), and Extended
Status register (Register 15). The status and control functions
defined here are considered basic and fundamental to 100 Mb/s and 1000
Mb/s PHYs. Registers 2 through 14 are part of the extended register
set. The format of Registers 4 through 10 are defined for the specific
Auto-Negotiation protocol used (Clause 28 or Clause 37). The format of
these registers is selected by the bit settings of Registers 1 and 15.

So clause 29 is not making much sense here. Can anybody explain it?

> +static int oa_tc6_mdiobus_register(struct oa_tc6 *tc6)
> +{
> +	int ret;
> +
> +	tc6->mdiobus = mdiobus_alloc();
> +	if (!tc6->mdiobus) {
> +		netdev_err(tc6->netdev, "MDIO bus alloc failed\n");
> +		return -ENODEV;
> +	}
> +
> +	tc6->mdiobus->priv = tc6;
> +	tc6->mdiobus->read = oa_tc6_mdiobus_direct_read;
> +	tc6->mdiobus->write = oa_tc6_mdiobus_direct_write;

This might get answered in later patches. PLCA registers are in C45
address space, VEND1 if i remember correctly. You don't provide any
C45 access methods here. Does TC6 specify that C45 over C22 must be
implemented?

The standard does say:

Vendor specific registers may be mapped into MMS 10 though MMS
15. When directly mapped, PHY vendor specific registers in MMD 30 or
MMD 31 would be mapped into the vendor specific MMS 10 through MMS 15.

So i'm thinking you might need to provide C45 access, at least MMD 30,
via MMS 10-15?

    Andrew