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Message-ID: <33e001da7033$e6a13ae0$b3e3b0a0$@samsung.com> Date: Thu, 7 Mar 2024 07:35:14 +0530 From: "Alim Akhtar" <alim.akhtar@...sung.com> To: "'Tudor Ambarus'" <tudor.ambarus@...aro.org>, "'Sylwester Nawrocki'" <s.nawrocki@...sung.com>, "'Chanwoo Choi'" <cw00.choi@...sung.com> Cc: "'Sam Protsenko'" <semen.protsenko@...aro.org>, "'Krzysztof Kozlowski'" <krzysztof.kozlowski@...aro.org>, <linux-samsung-soc@...r.kernel.org>, <linux-clk@...r.kernel.org>, <linux-kernel@...r.kernel.org>, "'linux-arm-kernel'" <linux-arm-kernel@...ts.infradead.org>, "'Peter Griffin'" <peter.griffin@...aro.org>, 'André Draszik' <andre.draszik@...aro.org>, "'William McVicker'" <willmcvicker@...gle.com>, <kernel-team@...roid.com>, <jaewon02.kim@...sung.com> Subject: RE: samsung: clk: re-parent MUX to OSCCLK at run-time Hi Tudor > -----Original Message----- > From: Tudor Ambarus <tudor.ambarus@...aro.org> > Sent: Wednesday, March 6, 2024 11:40 AM > To: Alim Akhtar <alim.akhtar@...sung.com>; 'Sylwester Nawrocki' > <s.nawrocki@...sung.com>; 'Chanwoo Choi' <cw00.choi@...sung.com> > Cc: 'Sam Protsenko' <semen.protsenko@...aro.org>; 'Krzysztof Kozlowski' > <krzysztof.kozlowski@...aro.org>; linux-samsung-soc@...r.kernel.org; > linux-clk@...r.kernel.org; linux-kernel@...r.kernel.org; 'linux-arm-kernel' > <linux-arm-kernel@...ts.infradead.org>; 'Peter Griffin' > <peter.griffin@...aro.org>; 'André Draszik' <andre.draszik@...aro.org>; > 'William McVicker' <willmcvicker@...gle.com>; kernel-team@...roid.com; > jaewon02.kim@...sung.com > Subject: Re: samsung: clk: re-parent MUX to OSCCLK at run-time > > > > On 3/6/24 04:49, Alim Akhtar wrote: > > Hi Tudor > > Hi! > > > > >> -----Original Message----- > >> From: Tudor Ambarus <tudor.ambarus@...aro.org> > >> Sent: Wednesday, March 6, 2024 8:50 AM > >> To: Sylwester Nawrocki <s.nawrocki@...sung.com>; Chanwoo Choi > >> <cw00.choi@...sung.com>; Alim Akhtar <alim.akhtar@...sung.com> > >> Cc: Sam Protsenko <semen.protsenko@...aro.org>; Krzysztof Kozlowski > >> <krzysztof.kozlowski@...aro.org>; linux-samsung-soc@...r.kernel.org; > >> linux-clk@...r.kernel.org; linux-kernel@...r.kernel.org; > >> linux-arm-kernel <linux-arm-kernel@...ts.infradead.org>; Peter > >> Griffin <peter.griffin@...aro.org>; André Draszik > >> <andre.draszik@...aro.org>; William McVicker > >> <willmcvicker@...gle.com>; kernel-team@...roid.com > >> Subject: samsung: clk: re-parent MUX to OSCCLK at run-time > >> > >> Hi, > >> > >> Trying to get some feedback from the samsung experts. Please consider > >> the > >> following: > >> > >> --------------------------------------------- > >> | CMU_PERIC0 | > >> | | > >> | MUX_USI | > >> | | > >> | |\ | > >> OSCCLK ---|->| \ | > >> | | \ | > >> | | M | | > >> | | U |--> DIV_CLK_PERIC0_USI*_ --> GATE_USI | > >> | | X | (1 ~ 16) | > >> | | / | > >> DIV_CLKCMU_PERIC0_IP ---|->| / | > >> (1 ~ 16) | | |/ | > >> | | | > >> | | | > >> | | MUX_I3C | > >> | | | > >> | | |\ | > >> --|->| \ | > >> | | \ | > >> | | M | | > >> | | U |--> DIV_CLK_PERIC0_I3C --> GATE_I3C | > >> | | X | | > >> | | / | > >> OSCCLK ---|->| / | > >> | |/ | > >> | | > >> > >> --------------------------------------------- > >> > >> Is it fine to re-parent the MUX_USI from above to OSCCLK at run-time, > > > > I am not aware of the exact SOC/HW you are working on. > > I'm working with GS101. I'm interested in exynos850 as well. > > > It depends on the CMU design about how to achieve low power mode and > clock gating for an IP/Block. > > > > In theory and looking at your clock diagram above, it is ok to switch to > OSCCLK for MUX_USI. > > > > If you can just use GATE_USI clock to clock gate USI IP, you will have a low > power for USI (of course there will be a leakage current still drawn). > > Is that what you want to achieve (low power mode)? Or you are looking to > get lowest possible operating clock for USI IP? > > I'm trying to get the lowest possible operating clock for the USI IP. > > > > > You need to takecare about if that clock is being shared with any > > other IP, > > It's not shared, the entire MUX USI, DIV, and GATE sequence is dedicated > per IP. GS101 has 15 USI blocks, each with its dedicated MUX-DIV-GATE > sequence of clocks. > > > so unless all the IPs which consume this clock, goes into idle state, you can > avoid MUX_USI change to OSCCLK. > > Since the MUX USI is per IP, I guess I shouldn't be concerned about this, > right? Yes, that should be fine > > I'm trying to find out if it's OK to reparent the MUX to OSCCLK in normal > operation mode (not low power mode), in order to get the lowest possible > operating clock for the USI IP. Would be great if the decision is backed up by > some info from datasheet. Unfortunately the datasheet that I have access to > it's not explicit. > Unfortunately, I don't have access to either of the datasheets. So won't be able to provide input from datasheet. Looking at your explanation above, like MUX USI is per IP, so it okay to switch to OSCCLK to get lowest possible clock for USI. You need to do some more regression test with this change (I would still suggest to reach out to GS101 team to get the confirmation of any other side effect) For me, it looks ok to use OSCCLK for USI > Thanks for the help! > ta > > >
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