linux-kernel - Re: [PATCH 2/5] clk: qcom: clk-alpha-pll: Add support for Regera PLL ops

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <1e353c1a-e267-14d0-fdf4-36aea9062ed3@quicinc.com>
Date: Fri, 8 Mar 2024 13:56:51 +0530
From: "Satya Priya Kakitapalli (Temp)" <quic_skakitap@...cinc.com>
To: Konrad Dybcio <konrad.dybcio@...aro.org>,
        Bjorn Andersson
	<andersson@...nel.org>,
        Michael Turquette <mturquette@...libre.com>,
        "Stephen
 Boyd" <sboyd@...nel.org>,
        Abhishek Sahu <absahu@...eaurora.org>, Rob Herring
	<robh@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Conor Dooley <conor+dt@...nel.org>
CC: Stephen Boyd <sboyd@...eaurora.org>, <linux-arm-msm@...r.kernel.org>,
        <linux-clk@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        <devicetree@...r.kernel.org>, Ajit Pandey <quic_ajipan@...cinc.com>,
        "Imran
 Shaik" <quic_imrashai@...cinc.com>,
        Taniya Das <quic_tdas@...cinc.com>,
        Jagadeesh Kona <quic_jkona@...cinc.com>
Subject: Re: [PATCH 2/5] clk: qcom: clk-alpha-pll: Add support for Regera PLL
 ops


On 3/2/2024 5:26 AM, Konrad Dybcio wrote:
> On 29.02.2024 06:38, Satya Priya Kakitapalli wrote:
>> From: Taniya Das <quic_tdas@...cinc.com>
>>
>> Regera PLL ops are required to control the Regera PLL from clock
>> controller drivers, thus add support for the same.
>>
>> Signed-off-by: Taniya Das <quic_tdas@...cinc.com>
>> Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@...cinc.com>
>> ---
> [...]
>
>
>> +static int clk_regera_pll_enable(struct clk_hw *hw)
> This function is 1:1 clk_zonda_pll_enable() logic-wise, except for
> the `if (val & ZONDA_STAY_IN_CFA)` part. Would it be an issue on
> Regera?


Yes, that is only applicable for Zonda PLL, hence we cannot re-use the 
same code for Regera.


>> +static void clk_regera_pll_disable(struct clk_hw *hw)
> This again is clk_zonda_pll_disable(), except the very last value written
> to PLL_OPMODE is different. Could you commonize them?
>

This difference is there between Zonda and regera PLLs as per the HW 
recommendation, hence we cannot re-use this.


>> +
>> +static void zonda_pll_adjust_l_val(unsigned long rate, unsigned long prate,
>> +									u32 *l)
> (Ugly wrapping, please touch it up)
>
> ..should it apply to zonda as the name suggests? Also, any explanations?


Yes, it is applicable for Zonda PLL as well, will update the Zonda pll 
set rate in next post. The L value needs to be adjusted to handle the 16 
bit signed alpha.


>> +	u64 remainder, quotient;
>> +
>> +	quotient = rate;
>> +	remainder = do_div(quotient, prate);
>> +	*l = quotient;
>> +
>> +	if ((remainder * 2) / prate)
>> +		*l = *l + 1;
>> +}
>> +
>> +static int clk_regera_pll_set_rate(struct clk_hw *hw, unsigned long rate,
>> +				  unsigned long prate)
>> +{
>> +	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
>> +	unsigned long rrate;
>> +	u32 l, alpha_width = pll_alpha_width(pll);
>> +	u64 a;
>> +	int ret;
>> +
>> +	rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
>> +
>> +	ret = alpha_pll_check_rate_margin(hw, rrate, rate);
>> +	if (ret < 0)
>> +		return ret;
>> +
>> +	if (a && (a & BIT(15)))
> What is BIT(15)?
>
> Also, the left part of the condition is totally bogus, if a is 0 then
> a & BIT(15) will surely be zero as well.


Sure, will correct this.


> Konrad
>
>