linux-kernel - Re: [PATCH 12/18] ASoC: codecs: mt6357: add MT6357 codec

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Date: Tue, 12 Mar 2024 15:54:55 +0100
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
To: Alexandre Mergnat <amergnat@...libre.com>
Cc: Flora Fu <flora.fu@...iatek.com>, Liam Girdwood <lgirdwood@...il.com>,
 Lee Jones <lee@...nel.org>, Rob Herring <robh+dt@...nel.org>,
 Mark Brown <broonie@...nel.org>, Matthias Brugger <matthias.bgg@...il.com>,
 Conor Dooley <conor+dt@...nel.org>,
 Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
 Catalin Marinas <catalin.marinas@....com>,
 Christian König <christian.koenig@....com>,
 Sumit Semwal <sumit.semwal@...aro.org>, Takashi Iwai <tiwai@...e.com>,
 Jaroslav Kysela <perex@...ex.cz>, Will Deacon <will@...nel.org>,
 linux-sound@...r.kernel.org, devicetree@...r.kernel.org,
 linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
 linux-mediatek@...ts.infradead.org, linux-media@...r.kernel.org,
 dri-devel@...ts.freedesktop.org, linaro-mm-sig@...ts.linaro.org,
 Nicolas Belin <nbelin@...libre.com>
Subject: Re: [PATCH 12/18] ASoC: codecs: mt6357: add MT6357 codec

Il 12/03/24 15:50, Alexandre Mergnat ha scritto:
> 
> 
> On 26/02/2024 16:25, AngeloGioacchino Del Regno wrote:
>>> +    if (enable) {
>>> +        /* set gpio mosi mode */
>>> +        regmap_write(priv->regmap, MT6357_GPIO_MODE2_CLR, GPIO_MODE2_CLEAR_ALL);
>>> +        regmap_write(priv->regmap, MT6357_GPIO_MODE2_SET, 
>>> GPIO8_MODE_SET_AUD_CLK_MOSI |
>>> +                                  GPIO9_MODE_SET_AUD_DAT_MOSI0 |
>>> +                                  GPIO10_MODE_SET_AUD_DAT_MOSI1 |
>>> +                                  GPIO11_MODE_SET_AUD_SYNC_MOSI);
>>
>> Are you sure that you need to write to MODE2_SET *and* to MODE2?!
> 
> This is downstream code and these registers aren't in my documentation.
> I've removed the MODE2_SET write and test the audio: it's still working.
> 
> So I will keep the spurious write removed for v2. :)
> 

Usually, MediaTek registers are laid out like "REG" being R/legacy-W and
"REG_SET/CLR" for setting and clearing bits in "REG" internally, and that
might account for internal latencies and such.

Can you please try to remove the MODE2 write instead of the MODE2_SET one
and check if that works?

You're already using the SETCLR way when manipulating registers in here,
so I would confidently expect that to work.

Cheers,
Angelo