linux-kernel - Re: [PATCH v4 18/18] PCI: j721e: Add suspend and resume support

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Date: Wed, 13 Mar 2024 12:21:09 +0530
From: Siddharth Vadapalli <s-vadapalli@...com>
To: Thomas Richard <thomas.richard@...tlin.com>
CC: Linus Walleij <linus.walleij@...aro.org>,
        Bartosz Golaszewski
	<brgl@...ev.pl>,
        Andy Shevchenko <andy@...nel.org>, Tony Lindgren
	<tony@...mide.com>,
        Haojian Zhuang <haojian.zhuang@...aro.org>,
        Vignesh R
	<vigneshr@...com>, Aaro Koskinen <aaro.koskinen@....fi>,
        Janusz Krzysztofik
	<jmkrzyszt@...il.com>,
        Andi Shyti <andi.shyti@...nel.org>, Peter Rosin
	<peda@...ntia.se>,
        Vinod Koul <vkoul@...nel.org>,
        Kishon Vijay Abraham I
	<kishon@...nel.org>,
        Philipp Zabel <p.zabel@...gutronix.de>,
        Lorenzo
 Pieralisi <lpieralisi@...nel.org>,
        Krzysztof Wilczyński
	<kw@...ux.com>,
        Rob Herring <robh@...nel.org>, Bjorn Helgaas
	<bhelgaas@...gle.com>,
        <linux-gpio@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>, <linux-omap@...r.kernel.org>,
        <linux-i2c@...r.kernel.org>, <linux-phy@...ts.infradead.org>,
        <linux-pci@...r.kernel.org>, <gregory.clement@...tlin.com>,
        <theo.lebrun@...tlin.com>, <thomas.petazzoni@...tlin.com>,
        <u-kumar1@...com>, <s-vadapalli@...com>
Subject: Re: [PATCH v4 18/18] PCI: j721e: Add suspend and resume support

On Mon, Mar 04, 2024 at 04:36:01PM +0100, Thomas Richard wrote:
> From: Théo Lebrun <theo.lebrun@...tlin.com>
> 
> Add suspend and resume support. Only the rc mode is supported.
> 
> During the suspend stage PERST# is asserted, then deasserted during the
> resume stage.
> 
> Signed-off-by: Théo Lebrun <theo.lebrun@...tlin.com>
> Signed-off-by: Thomas Richard <thomas.richard@...tlin.com>

Reviewed-by: Siddharth Vadapalli <s-vadapalli@...com>

Regards,
Siddharth.

> ---
>  drivers/pci/controller/cadence/pci-j721e.c | 86 ++++++++++++++++++++++++++++++
>  1 file changed, 86 insertions(+)
> 
> diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
> index 9af4fd64c1f9..a1f1232e8ee5 100644
> --- a/drivers/pci/controller/cadence/pci-j721e.c
> +++ b/drivers/pci/controller/cadence/pci-j721e.c
> @@ -7,6 +7,8 @@
>   */
>  
>  #include <linux/clk.h>
> +#include <linux/clk-provider.h>
> +#include <linux/container_of.h>
>  #include <linux/delay.h>
>  #include <linux/gpio/consumer.h>
>  #include <linux/io.h>
> @@ -22,6 +24,8 @@
>  #include "../../pci.h"
>  #include "pcie-cadence.h"
>  
> +#define cdns_pcie_to_rc(p) container_of(p, struct cdns_pcie_rc, pcie)
> +
>  #define ENABLE_REG_SYS_2	0x108
>  #define STATUS_REG_SYS_2	0x508
>  #define STATUS_CLR_REG_SYS_2	0x708
> @@ -588,6 +592,87 @@ static void j721e_pcie_remove(struct platform_device *pdev)
>  	pm_runtime_disable(dev);
>  }
>  
> +static int j721e_pcie_suspend_noirq(struct device *dev)
> +{
> +	struct j721e_pcie *pcie = dev_get_drvdata(dev);
> +
> +	if (pcie->mode == PCI_MODE_RC) {
> +		gpiod_set_value_cansleep(pcie->reset_gpio, 0);
> +		clk_disable_unprepare(pcie->refclk);
> +	}
> +
> +	cdns_pcie_disable_phy(pcie->cdns_pcie);
> +
> +	return 0;
> +}
> +
> +static int j721e_pcie_resume_noirq(struct device *dev)
> +{
> +	struct j721e_pcie *pcie = dev_get_drvdata(dev);
> +	struct cdns_pcie *cdns_pcie = pcie->cdns_pcie;
> +	int ret;
> +
> +	ret = j721e_pcie_ctrl_init(pcie);
> +	if (ret < 0)
> +		return ret;
> +
> +	j721e_pcie_config_link_irq(pcie);
> +
> +	/*
> +	 * This is not called explicitly in the probe, it is called by
> +	 * cdns_pcie_init_phy().
> +	 */
> +	ret = cdns_pcie_enable_phy(pcie->cdns_pcie);
> +	if (ret < 0)
> +		return ret;
> +
> +	if (pcie->mode == PCI_MODE_RC) {
> +		struct cdns_pcie_rc *rc = cdns_pcie_to_rc(cdns_pcie);
> +
> +		ret = clk_prepare_enable(pcie->refclk);
> +		if (ret < 0)
> +			return ret;
> +
> +		/*
> +		 * "Power Sequencing and Reset Signal Timings" table in
> +		 * PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 3.0
> +		 * indicates PERST# should be deasserted after minimum of 100us
> +		 * once REFCLK is stable. The REFCLK to the connector in RC
> +		 * mode is selected while enabling the PHY. So deassert PERST#
> +		 * after 100 us.
> +		 */
> +		if (pcie->reset_gpio) {
> +			fsleep(100);
> +			gpiod_set_value_cansleep(pcie->reset_gpio, 1);
> +		}
> +
> +		ret = cdns_pcie_host_link_setup(rc);
> +		if (ret < 0) {
> +			clk_disable_unprepare(pcie->refclk);
> +			return ret;
> +		}
> +
> +		/*
> +		 * Reset internal status of BARs to force reinitialization in
> +		 * cdns_pcie_host_init().
> +		 */
> +		for (enum cdns_pcie_rp_bar bar = RP_BAR0; bar <= RP_NO_BAR; bar++)
> +			rc->avail_ib_bar[bar] = true;
> +
> +		ret = cdns_pcie_host_init(rc);
> +		if (ret) {
> +			clk_disable_unprepare(pcie->refclk);
> +			return ret;
> +		}
> +	}
> +
> +	return 0;
> +}
> +
> +static DEFINE_NOIRQ_DEV_PM_OPS(j721e_pcie_pm_ops,
> +			       j721e_pcie_suspend_noirq,
> +			       j721e_pcie_resume_noirq);
> +
>  static struct platform_driver j721e_pcie_driver = {
>  	.probe  = j721e_pcie_probe,
>  	.remove_new = j721e_pcie_remove,
> @@ -595,6 +680,7 @@ static struct platform_driver j721e_pcie_driver = {
>  		.name	= "j721e-pcie",
>  		.of_match_table = of_j721e_pcie_match,
>  		.suppress_bind_attrs = true,
> +		.pm	= pm_sleep_ptr(&j721e_pcie_pm_ops),
>  	},
>  };
>  builtin_platform_driver(j721e_pcie_driver);
> 
> -- 
> 2.39.2
> 
>