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Date: Thu, 14 Mar 2024 14:12:01 +0800
From: Joshua Yeong <joshua.yeong@...rfivetech.com>
To: paul.walmsley@...ive.com,
palmer@...belt.com,
aou@...s.berkeley.edu,
geert+renesas@...der.be,
joshua.yeong@...rfivetech.com,
prabhakar.mahadev-lad.rj@...renesas.com,
conor.dooley@...rochip.com,
alexghiti@...osinc.com,
evan@...osinc.com,
ajones@...tanamicro.com,
heiko@...ech.de,
guoren@...nel.org,
uwu@...nowy.me,
jszhang@...nel.org,
conor@...nel.org,
robh+dt@...nel.org,
krzysztof.kozlowski+dt@...aro.org,
conor+dt@...nel.org,
leyfoon.tan@...rfivetech.com,
jeeheng.sia@...rfivetech.com
Cc: linux-riscv@...ts.infradead.org,
linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org
Subject: [PATCH 0/4] Add StarFive's StarLink-500 Cache Controller
StarFive's StarLink-500 Cache Controller flush/invalidates cache using non-
conventional CMO method. This driver provides the cache handling on StarFive
RISC-V SoC.
Joshua Yeong (4):
riscv: asm: vendorid_list: Add StarFive Technology to vendors list
riscv: errata: Add StarFive alternative ports
cache: Add StarLink-500 cache management for StarFive JH8100 RISC-V
core
dt-bindings: cache: Add docs for StarFive StarLink-500 cache
controller
.../cache/starfive,starlink-500-cache.yaml | 62 ++++++++
arch/riscv/Kconfig.errata | 21 +++
arch/riscv/errata/Makefile | 1 +
arch/riscv/errata/starfive/Makefile | 1 +
arch/riscv/errata/starfive/errata.c | 95 ++++++++++++
arch/riscv/include/asm/alternative.h | 3 +
arch/riscv/include/asm/errata_list.h | 5 +
arch/riscv/include/asm/vendorid_list.h | 1 +
arch/riscv/kernel/alternative.c | 5 +
drivers/cache/Kconfig | 9 ++
drivers/cache/Makefile | 1 +
drivers/cache/starlink500_cache.c | 137 ++++++++++++++++++
12 files changed, 341 insertions(+)
create mode 100644 Documentation/devicetree/bindings/cache/starfive,starlink-500-cache.yaml
create mode 100644 arch/riscv/errata/starfive/Makefile
create mode 100644 arch/riscv/errata/starfive/errata.c
create mode 100644 drivers/cache/starlink500_cache.c
--
2.25.1
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