linux-kernel - RE: [PATCH] riscv: Do not save the scratch CSR during suspend

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Date: Fri, 15 Mar 2024 04:55:57 +0000
From: JeeHeng Sia <jeeheng.sia@...rfivetech.com>
To: Samuel Holland <samuel.holland@...ive.com>, Palmer Dabbelt
	<palmer@...belt.com>, "linux-riscv@...ts.infradead.org"
	<linux-riscv@...ts.infradead.org>
CC: Albert Ou <aou@...s.berkeley.edu>, Andrew Jones <ajones@...tanamicro.com>,
	Conor Dooley <conor.dooley@...rochip.com>, Leyfoon Tan
	<leyfoon.tan@...rfivetech.com>, Paul Walmsley <paul.walmsley@...ive.com>,
	Pavel Machek <pavel@....cz>, "Rafael J. Wysocki" <rafael@...nel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"linux-pm@...r.kernel.org" <linux-pm@...r.kernel.org>
Subject: RE: [PATCH] riscv: Do not save the scratch CSR during suspend



> -----Original Message-----
> From: Samuel Holland <samuel.holland@...ive.com>
> Sent: Wednesday, March 13, 2024 3:57 AM
> To: Palmer Dabbelt <palmer@...belt.com>; linux-riscv@...ts.infradead.org
> Cc: Samuel Holland <samuel.holland@...ive.com>; Albert Ou <aou@...s.berkeley.edu>; Andrew Jones <ajones@...tanamicro.com>;
> Conor Dooley <conor.dooley@...rochip.com>; Leyfoon Tan <leyfoon.tan@...rfivetech.com>; Paul Walmsley
> <paul.walmsley@...ive.com>; Pavel Machek <pavel@....cz>; Rafael J. Wysocki <rafael@...nel.org>; JeeHeng Sia
> <jeeheng.sia@...rfivetech.com>; linux-kernel@...r.kernel.org; linux-pm@...r.kernel.org
> Subject: [PATCH] riscv: Do not save the scratch CSR during suspend
> 
> While the processor is executing kernel code, the value of the scratch
> CSR is always zero, so there is no need to save the value. Continue to
> write the CSR during the resume flow, so we do not rely on firmware to
> initialize it.
> 
> Signed-off-by: Samuel Holland <samuel.holland@...ive.com>
> ---
> 
>  arch/riscv/include/asm/suspend.h | 1 -
>  arch/riscv/kernel/suspend.c      | 3 +--
>  2 files changed, 1 insertion(+), 3 deletions(-)
> 
> diff --git a/arch/riscv/include/asm/suspend.h b/arch/riscv/include/asm/suspend.h
> index 491296a335d0..6569eefacf38 100644
> --- a/arch/riscv/include/asm/suspend.h
> +++ b/arch/riscv/include/asm/suspend.h
> @@ -13,7 +13,6 @@ struct suspend_context {
>  	/* Saved and restored by low-level functions */
>  	struct pt_regs regs;
>  	/* Saved and restored by high-level functions */
> -	unsigned long scratch;
>  	unsigned long envcfg;
>  	unsigned long tvec;
>  	unsigned long ie;
> diff --git a/arch/riscv/kernel/suspend.c b/arch/riscv/kernel/suspend.c
> index 299795341e8a..3d306d8a253d 100644
> --- a/arch/riscv/kernel/suspend.c
> +++ b/arch/riscv/kernel/suspend.c
> @@ -14,7 +14,6 @@
> 
>  void suspend_save_csrs(struct suspend_context *context)
>  {
> -	context->scratch = csr_read(CSR_SCRATCH);
>  	if (riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_XLINUXENVCFG))
>  		context->envcfg = csr_read(CSR_ENVCFG);
>  	context->tvec = csr_read(CSR_TVEC);
> @@ -37,7 +36,7 @@ void suspend_save_csrs(struct suspend_context *context)
> 
>  void suspend_restore_csrs(struct suspend_context *context)
>  {
> -	csr_write(CSR_SCRATCH, context->scratch);
> +	csr_write(CSR_SCRATCH, 0);
If the register is always zero, do we need to explicitly write zero to the register during resume?
>  	if (riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_XLINUXENVCFG))
>  		csr_write(CSR_ENVCFG, context->envcfg);
>  	csr_write(CSR_TVEC, context->tvec);
> --
> 2.43.1