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Message-ID: <f9c380bf-05c4-4a24-9d42-5ad24b181e66@amlogic.com>
Date: Fri, 15 Mar 2024 09:16:03 +0800
From: Xianwei Zhao <xianwei.zhao@...ogic.com>
To: neil.armstrong@...aro.org, Dmitry Rokosov <ddrokosov@...utedevices.com>,
Xianwei Zhao via B4 Relay <devnull+xianwei.zhao.amlogic.com@...nel.org>
Cc: Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>,
Martin Blumenstingl <martin.blumenstingl@...glemail.com>,
Jerome Brunet <jbrunet@...libre.com>, Kevin Hilman <khilman@...libre.com>,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-amlogic@...ts.infradead.org
Subject: Re: [DMARC error][DKIM error] [PATCH 3/4] arm64: dts: add support for
A4 based Amlogic BA400
Hi Neil,
Thanks for your review.
On 2024/3/14 17:04, Neil Armstrong wrote:
> [ EXTERNAL EMAIL ]
>
> On 14/03/2024 06:19, Xianwei Zhao wrote:
>> Hi Dmitry,
>> Thanks for your review.
>>
>> On 2024/3/13 17:53, Dmitry Rokosov wrote:
>>> [????????? ddrokosov@...utedevices.com ?????????
>>> https://aka.ms/LearnAboutSenderIdentification?????????????]
>>>
>>> [ EXTERNAL EMAIL ]
>>>
>>> Hello Xianwei,
>>>
>>> On Tue, Mar 12, 2024 at 05:18:59PM +0800, Xianwei Zhao via B4 Relay
>>> wrote:
>>>> From: Xianwei Zhao <xianwei.zhao@...ogic.com>
>>>>
>>>> Amlogic A4 is an application processor designed for smart audio
>>>> and IoT applications.
>>>>
>>>> Add basic support for the A4 based Amlogic BA400 board, which describes
>>>> the following components: CPU, GIC, IRQ, Timer and UART.
>>>> These are capable of booting up into the serial console.
>>>>
>>>> Signed-off-by: Xianwei Zhao <xianwei.zhao@...ogic.com>
>>>> ---
>>>> arch/arm64/boot/dts/amlogic/Makefile | 1 +
>>>> .../boot/dts/amlogic/amlogic-a4-a113l2-ba400.dts | 43 ++++++++++
>>>> arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi | 99
>>>> ++++++++++++++++++++++
>>>> 3 files changed, 143 insertions(+)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/amlogic/Makefile
>>>> b/arch/arm64/boot/dts/amlogic/Makefile
>>>> index 1ab160bf928a..9a50ec11bb8d 100644
>>>> --- a/arch/arm64/boot/dts/amlogic/Makefile
>>>> +++ b/arch/arm64/boot/dts/amlogic/Makefile
>>>> @@ -1,4 +1,5 @@
>>>> # SPDX-License-Identifier: GPL-2.0
>>>> +dtb-$(CONFIG_ARCH_MESON) += amlogic-a4-a113l2-ba400.dtb
>>>> dtb-$(CONFIG_ARCH_MESON) += amlogic-c3-c302x-aw409.dtb
>>>> dtb-$(CONFIG_ARCH_MESON) += amlogic-t7-a311d2-an400.dtb
>>>> dtb-$(CONFIG_ARCH_MESON) += amlogic-t7-a311d2-khadas-vim4.dtb
>>>> diff --git a/arch/arm64/boot/dts/amlogic/amlogic-a4-a113l2-ba400.dts
>>>> b/arch/arm64/boot/dts/amlogic/amlogic-a4-a113l2-ba400.dts
>>>> new file mode 100644
>>>> index 000000000000..60f9f23858c6
>>>> --- /dev/null
>>>> +++ b/arch/arm64/boot/dts/amlogic/amlogic-a4-a113l2-ba400.dts
>>>> @@ -0,0 +1,43 @@
>>>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>>>> +/*
>>>> + * Copyright (c) 2024 Amlogic, Inc. All rights reserved.
>>>> + */
>>>> +
>>>> +/dts-v1/;
>>>> +
>>>> +#include "amlogic-a4.dtsi"
>>>> +
>>>> +/ {
>>>> + model = "Amlogic A113L2 ba400 Development Board";
>>>> + compatible = "amlogic,ba400","amlogic,a4";
>>>> + interrupt-parent = <&gic>;
>>>> + #address-cells = <2>;
>>>> + #size-cells = <2>;
>>>> +
>>>> + aliases {
>>>> + serial0 = &uart_b;
>>>> + };
>>>> +
>>>> + memory@0 {
>>>> + device_type = "memory";
>>>> + reg = <0x0 0x0 0x0 0x40000000>;
>>>> + };
>>>> +
>>>> + reserved-memory {
>>>> + #address-cells = <2>;
>>>> + #size-cells = <2>;
>>>> + ranges;
>>>> +
>>>> + /* 52 MiB reserved for ARM Trusted Firmware */
>>>> + secmon_reserved:linux,secmon {
>>>> + compatible = "shared-dma-pool";
>>>> + no-map;
>>>> + alignment = <0x0 0x400000>;
>>>> + reg = <0x0 0x05000000 0x0 0x3400000>;
>>>> + };
>>>> + };
>>>> +};
>>>> +
>>>> +&uart_b {
>>>> + status = "okay";
>>>> +};
>>>> diff --git a/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi
>>>> b/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi
>>>> new file mode 100644
>>>> index 000000000000..7e8745010b52
>>>> --- /dev/null
>>>> +++ b/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi
>>>> @@ -0,0 +1,99 @@
>>>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>>>> +/*
>>>> + * Copyright (c) 2024 Amlogic, Inc. All rights reserved.
>>>> + */
>>>> +
>>>> +#include <dt-bindings/interrupt-controller/irq.h>
>>>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>>>> +#include <dt-bindings/gpio/gpio.h>
>>>> +/ {
>>>> + cpus {
>>>> + #address-cells = <2>;
>>>> + #size-cells = <0>;
>>>> +
>>>> + cpu0: cpu@0 {
>>>> + device_type = "cpu";
>>>> + compatible = "arm,cortex-a53";
>>>> + reg = <0x0 0x0>;
>>>> + enable-method = "psci";
>>>> + };
>>>> +
>>>> + cpu1: cpu@1 {
>>>> + device_type = "cpu";
>>>> + compatible = "arm,cortex-a53";
>>>> + reg = <0x0 0x1>;
>>>> + enable-method = "psci";
>>>> + };
>>>> +
>>>> + cpu2: cpu@2 {
>>>> + device_type = "cpu";
>>>> + compatible = "arm,cortex-a53";
>>>> + reg = <0x0 0x2>;
>>>> + enable-method = "psci";
>>>> + };
>>>> +
>>>> + cpu3: cpu@3 {
>>>> + device_type = "cpu";
>>>> + compatible = "arm,cortex-a53";
>>>> + reg = <0x0 0x3>;
>>>> + enable-method = "psci";
>>>> + };
>>>> + };
>>>> +
>>>> + timer {
>>>> + compatible = "arm,armv8-timer";
>>>> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
>>>> IRQ_TYPE_LEVEL_LOW)>,
>>>> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
>>>> IRQ_TYPE_LEVEL_LOW)>,
>>>> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
>>>> IRQ_TYPE_LEVEL_LOW)>,
>>>> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
>>>> IRQ_TYPE_LEVEL_LOW)>;
>>>> + };
>>>> +
>>>> + psci {
>>>> + compatible = "arm,psci-0.2";
>>>> + method = "smc";
>>>> + };
>>>> +
>>>> + xtal: xtal-clk {
>>>> + compatible = "fixed-clock";
>>>> + clock-frequency = <24000000>;
>>>> + clock-output-names = "xtal";
>>>> + #clock-cells = <0>;
>>>> + };
>>>> +
>>>> + soc {
>>>> + compatible = "simple-bus";
>>>> + #address-cells = <2>;
>>>> + #size-cells = <2>;
>>>> + ranges;
>>>> +
>>>> + gic: interrupt-controller@...01000 {
>>>> + compatible = "arm,gic-400";
>>>> + #interrupt-cells = <3>;
>>>> + #address-cells = <0>;
>>>> + interrupt-controller;
>>>> + reg = <0x0 0xfff01000 0 0x1000>,
>>>> + <0x0 0xfff02000 0 0x2000>,
>>>> + <0x0 0xfff04000 0 0x2000>,
>>>> + <0x0 0xfff06000 0 0x2000>;
>>>> + interrupts = <GIC_PPI 9
>>>> (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
>>>> + };
>>>> +
>>>> + apb@...00000 {
>>>> + compatible = "simple-bus";
>>>> + reg = <0x0 0xfe000000 0x0 0x480000>;
>>>> + #address-cells = <2>;
>>>> + #size-cells = <2>;
>>>> + ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>;
>>>> +
>>>> + uart_b: serial@...00 {
>>>> + compatible = "amlogic,meson-s4-uart",
>>>
>>> If I'm not wrong, you need to create dt-binding alias for meson-a4-uart
>>> and use it as 3rd compatible string.
>
> Please add an A4 and A5 compatible using amlogic,meson-s4-uart as fallback,
> and drop the ao-uart since there's no more AO uart.
>
> Follow how it was done for the T7 in
> Documentation/devicetree/bindings/serial/amlogic,meson-uart.yaml
>
> The amlogic,meson-s4-uart will provide an earlycon like ao-uart did.
>
Will do.
> Thanks,
> Neil
>
>>>
>> On UART module, A4 and A5 SoCs exactly the same as S4. There's no
>> difference.
>>>> + "amlogic,meson-ao-uart";
>>>> + reg = <0x0 0x7a000 0x0 0x18>;
>>>> + interrupts = <GIC_SPI 169
>>>> IRQ_TYPE_EDGE_RISING>;
>>>> + clocks = <&xtal>, <&xtal>, <&xtal>;
>>>> + clock-names = "xtal", "pclk", "baud";
>>>> + status = "disabled";
>>>> + };
>>>> + };
>>>> + };
>>>> +};
>>>>
>>>> --
>>>> 2.37.1
>>>>
>>>>
>>>> _______________________________________________
>>>> linux-amlogic mailing list
>>>> linux-amlogic@...ts.infradead.org
>>>> http://lists.infradead.org/mailman/listinfo/linux-amlogic
>>>
>>> --
>>> Thank you,
>>> Dmitry
>
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