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Message-ID:
 <PH7PR12MB5596A1DD75348ECC68EBBEFE93282@PH7PR12MB5596.namprd12.prod.outlook.com>
Date: Fri, 15 Mar 2024 12:19:06 +0000
From: "Khatri, Sunil" <Sunil.Khatri@....com>
To: "Khatri, Sunil" <Sunil.Khatri@....com>, "Deucher, Alexander"
	<Alexander.Deucher@....com>, "Koenig, Christian" <Christian.Koenig@....com>,
	"Sharma, Shashank" <Shashank.Sharma@....com>
CC: "amd-gfx@...ts.freedesktop.org" <amd-gfx@...ts.freedesktop.org>,
	"dri-devel@...ts.freedesktop.org" <dri-devel@...ts.freedesktop.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: RE: [PATCH] drm/amdgpu: add the hw_ip version of all IP's

[AMD Official Use Only - General]

Hello Alex

Added the information directly from the ip_version and also added names for each ip so the version information makes more sense to the user.

Below is the output in devcoredump now:
IP Information
SOC Family: 143
SOC Revision id: 0
SOC External Revision id: 50
HWIP: GC[1][0]: v10.3.2.0.0
HWIP: HDP[2][0]: v5.0.3.0.0
HWIP: SDMA0[3][0]: v5.2.2.0.0
HWIP: SDMA1[4][0]: v5.2.2.0.0
HWIP: MMHUB[12][0]: v2.1.0.0.0
HWIP: ATHUB[13][0]: v2.1.0.0.0
HWIP: NBIO[14][0]: v3.3.1.0.0
HWIP: MP0[15][0]: v11.0.11.0.0
HWIP: MP1[16][0]: v11.0.11.0.0
HWIP: UVD/JPEG/VCN[17][0]: v3.0.0.0.0
HWIP: UVD/JPEG/VCN[17][1]: v3.0.1.0.0
HWIP: DF[21][0]: v3.7.3.0.0
HWIP: DCE[22][0]: v3.0.0.0.0
HWIP: OSSSYS[23][0]: v5.0.3.0.0
HWIP: SMUIO[24][0]: v11.0.6.0.0
HWIP: NBIF[26][0]: v3.3.1.0.0
HWIP: THM[27][0]: v11.0.5.0.0
HWIP: CLK[28][0]: v11.0.3.0.0
HWIP: CLK[28][1]: v11.0.3.0.0
HWIP: CLK[28][2]: v11.0.3.0.0
HWIP: CLK[28][3]: v11.0.3.0.0
HWIP: CLK[28][4]: v11.0.3.0.0
HWIP: CLK[28][5]: v11.0.3.0.0
HWIP: CLK[28][6]: v11.0.3.0.0
HWIP: CLK[28][7]: v11.0.3.0.0
HWIP: UMC[29][0]: v8.7.1.0.0
HWIP: UMC[29][1]: v8.7.1.0.0
HWIP: UMC[29][2]: v8.7.1.0.0
HWIP: UMC[29][3]: v8.7.1.0.0
HWIP: UMC[29][4]: v8.7.1.0.0
HWIP: UMC[29][5]: v8.7.1.0.0
HWIP: PCIE[33][0]: v6.5.0.0.0


-----Original Message-----
From: Sunil Khatri <sunil.khatri@....com>
Sent: Friday, March 15, 2024 5:43 PM
To: Deucher, Alexander <Alexander.Deucher@....com>; Koenig, Christian <Christian.Koenig@....com>; Sharma, Shashank <Shashank.Sharma@....com>
Cc: amd-gfx@...ts.freedesktop.org; dri-devel@...ts.freedesktop.org; linux-kernel@...r.kernel.org; Khatri, Sunil <Sunil.Khatri@....com>
Subject: [PATCH] drm/amdgpu: add the hw_ip version of all IP's

Add all the IP's version information on a SOC to the devcoredump.

Signed-off-by: Sunil Khatri <sunil.khatri@....com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c | 62 +++++++++++++++++++++++
 1 file changed, 62 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
index a0dbccad2f53..3d4bfe0a5a7c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
@@ -29,6 +29,43 @@
 #include "sienna_cichlid.h"
 #include "smu_v13_0_10.h"

+const char *hw_ip_names[MAX_HWIP] = {
+       [GC_HWIP]               = "GC",
+       [HDP_HWIP]              = "HDP",
+       [SDMA0_HWIP]            = "SDMA0",
+       [SDMA1_HWIP]            = "SDMA1",
+       [SDMA2_HWIP]            = "SDMA2",
+       [SDMA3_HWIP]            = "SDMA3",
+       [SDMA4_HWIP]            = "SDMA4",
+       [SDMA5_HWIP]            = "SDMA5",
+       [SDMA6_HWIP]            = "SDMA6",
+       [SDMA7_HWIP]            = "SDMA7",
+       [LSDMA_HWIP]            = "LSDMA",
+       [MMHUB_HWIP]            = "MMHUB",
+       [ATHUB_HWIP]            = "ATHUB",
+       [NBIO_HWIP]             = "NBIO",
+       [MP0_HWIP]              = "MP0",
+       [MP1_HWIP]              = "MP1",
+       [UVD_HWIP]              = "UVD/JPEG/VCN",
+       [VCN1_HWIP]             = "VCN1",
+       [VCE_HWIP]              = "VCE",
+       [VPE_HWIP]              = "VPE",
+       [DF_HWIP]               = "DF",
+       [DCE_HWIP]              = "DCE",
+       [OSSSYS_HWIP]           = "OSSSYS",
+       [SMUIO_HWIP]            = "SMUIO",
+       [PWR_HWIP]              = "PWR",
+       [NBIF_HWIP]             = "NBIF",
+       [THM_HWIP]              = "THM",
+       [CLK_HWIP]              = "CLK",
+       [UMC_HWIP]              = "UMC",
+       [RSMU_HWIP]             = "RSMU",
+       [XGMI_HWIP]             = "XGMI",
+       [DCI_HWIP]              = "DCI",
+       [PCIE_HWIP]             = "PCIE",
+};
+
+
 int amdgpu_reset_init(struct amdgpu_device *adev)  {
        int ret = 0;
@@ -196,6 +233,31 @@ amdgpu_devcoredump_read(char *buffer, loff_t offset, size_t count,
                           coredump->reset_task_info.process_name,
                           coredump->reset_task_info.pid);

+       /* GPU IP's information of the SOC */
+       if (coredump->adev) {
+
+               drm_printf(&p, "\nIP Information\n");
+               drm_printf(&p, "SOC Family: %d\n", coredump->adev->family);
+               drm_printf(&p, "SOC Revision id: %d\n", coredump->adev->rev_id);
+               drm_printf(&p, "SOC External Revision id: %d\n",
+                          coredump->adev->external_rev_id);
+
+               for (int i = 1; i < MAX_HWIP; i++) {
+                       for (int j = 0; j < HWIP_MAX_INSTANCE; j++) {
+                               int ver = coredump->adev->ip_versions[i][j];
+
+                               if (ver)
+                                       drm_printf(&p, "HWIP: %s[%d][%d]: v%d.%d.%d.%d.%d\n",
+                                                  hw_ip_names[i], i, j,
+                                                  IP_VERSION_MAJ(ver),
+                                                  IP_VERSION_MIN(ver),
+                                                  IP_VERSION_REV(ver),
+                                                  IP_VERSION_VARIANT(ver),
+                                                  IP_VERSION_SUBREV(ver));
+                       }
+               }
+       }
+
        if (coredump->ring) {
                drm_printf(&p, "\nRing timed out details\n");
                drm_printf(&p, "IP Type: %d Ring Name: %s\n",
--
2.34.1


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