lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-ID: <ZfSRO9JeFTxEeM8Q@arm.com>
Date: Fri, 15 Mar 2024 18:19:39 +0000
From: Catalin Marinas <catalin.marinas@....com>
To: Palmer Dabbelt <palmer@...belt.com>
Cc: Stephen Rothwell <sfr@...b.auug.org.au>, Paul Walmsley <paul@...an.com>,
	Will Deacon <will@...nel.org>, jisheng.teoh@...rfivetech.com,
	linux-kernel@...r.kernel.org, linux-next@...r.kernel.org,
	locus84@...estech.com, peterlin@...estech.com
Subject: Re: linux-next: manual merge of the risc-v tree with the arm64 tree

On Fri, Mar 15, 2024 at 10:21:13AM -0700, Palmer Dabbelt wrote:
> On Thu, 14 Mar 2024 16:31:46 PDT (-0700), Stephen Rothwell wrote:
> > Hi all,
> > 
> > Today's linux-next merge of the risc-v tree got a conflict in:
> > 
> >   drivers/perf/Kconfig
> > 
> > between commits:
> > 
> >   c2b24812f7bc ("perf: starfive: Add StarLink PMU support")
> >   f0dbc6d0de38 ("perf: starfive: Only allow COMPILE_TEST for 64-bit architectures")
> > 
> > from the arm64 tree and commit:
> > 
> >   bc969d6cc96a ("perf: RISC-V: Introduce Andes PMU to support perf event sampling")
> > 
> > from the risc-v tree.
> > 
> > I fixed it up (see below) and can carry the fix as necessary. This
> > is now fixed as far as linux-next is concerned, but any non trivial
> > conflicts should be mentioned to your upstream maintainer when your tree
> > is submitted for merging.  You may also want to consider cooperating
> > with the maintainer of the conflicting tree to minimise any particularly
> > complex conflicts.
> 
> Sorry, I guess maybe I should have looked at my queue before agreeing to
> send the starfive PMU patches via the arm64 tree.  The Andes stuff touches a
> bunch of other RISC-V bits, but I'm happy to do a shared tag or something if
> folks want.
> 
> Otherwise I'll just point this out to Linus when I send my PR -- I'm going
> to hold off on that this morning, as I just realized I should have taken
> this GUP fix and thus want to let things bake a little longer.

The arm64 tree went in yesterday already. If you want, you can merge
the arm64 for-next/perf tree into yours before sending the PR to Linus.
Otherwise, the conflict is trivial, just give Linus a heads-up.

-- 
Catalin

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ