linux-kernel - Re: [RFC PATCH 0/6] Add support for root port RAS error handling

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <65f491b64f15a_aa2229497@dwillia2-mobl3.amr.corp.intel.com.notmuch>
Date: Fri, 15 Mar 2024 11:21:42 -0700
From: Dan Williams <dan.j.williams@...el.com>
To: "Li, Ming" <ming4.li@...el.com>, Dan Williams <dan.j.williams@...el.com>,
	<rrichter@....com>, <terry.bowman@....com>
CC: <linux-cxl@...r.kernel.org>, <linux-kernel@...r.kernel.org>
Subject: Re: [RFC PATCH 0/6] Add support for root port RAS error handling

Li, Ming wrote:
[..]
> > I do expect direct-attach to be a predominant use case, but I want to
> > make sure that the implementation at least does not make the switch port
> > error handling case more difficult to implement.
> 
> Hi Dan,
> 
> Currently, A rough idea I have is that:
> If a CXL switch connected to the CXL RP, there should be two cases,
> 1. no CXL memory device connected to the switch, in this case, I'm not
> sure whether CXL.cachemem protocol errors is still possibly happened
> between RP and switch without CXL memory device. If not, maybe we
> don't need to consider such case?

Protocol errors can happen between any 2 ports, just like PCI protocol
errors.

> 2. a CXL memory device connected to the switch. I think cxl_pci error
> handler could also help to handle CXL.cachemem protocol errors
> happened in switch USP/DSP.

No, for 2 reasons:

* The cxl_pci driver is only for general CXL type-3 memory
  expanders. Even though no CXL.cache devices have upstream drivers they
  do exist and they would experience protocol errors that the PCI core
  needs to consider.

* When a switch is present it is possible to have a protocol error
  between the switch upstream port and the root port, and not between
  the switch downstream port and the endpoint.

The more I think about it I do not think it is appropriate for cxl_pci
to be involved in clearing root port errors in the VH case, it only
works the RCH case because of the way the device and the root-port get
combined.