linux-kernel - [PATCH 13/14] mips: dts: ralink: mt7621: reorder pci?

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Message-Id: <20240316045442.31469-14-justin.swartz@risingedge.co.za>
Date: Sat, 16 Mar 2024 06:54:41 +0200
From: Justin Swartz <justin.swartz@...ingedge.co.za>
To: Arınç ÜNAL <arinc.unal@...nc9.com>,
	Sergio Paracuellos <sergio.paracuellos@...il.com>,
	Rob Herring <robh+dt@...nel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
	Conor Dooley <conor+dt@...nel.org>,
	Thomas Bogendoerfer <tsbogend@...ha.franken.de>,
	Matthias Brugger <matthias.bgg@...il.com>,
	AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
Cc: linux-mips@...r.kernel.org,
	devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org,
	linux-arm-kernel@...ts.infradead.org,
	linux-mediatek@...ts.infradead.org,
	Justin Swartz <justin.swartz@...ingedge.co.za>
Subject: [PATCH 13/14] mips: dts: ralink: mt7621: reorder pci?_phy attributes

Reorder the attributes of the PCIe PHY nodes node to match
what the DTS style guide recommends.

Signed-off-by: Justin Swartz <justin.swartz@...ingedge.co.za>
---
 arch/mips/boot/dts/ralink/mt7621.dtsi | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/arch/mips/boot/dts/ralink/mt7621.dtsi b/arch/mips/boot/dts/ralink/mt7621.dtsi
index aa06d12ac..284811f32 100644
--- a/arch/mips/boot/dts/ralink/mt7621.dtsi
+++ b/arch/mips/boot/dts/ralink/mt7621.dtsi
@@ -583,14 +583,18 @@ pcie@2,0 {
 	pcie0_phy: pcie-phy@...49000 {
 		compatible = "mediatek,mt7621-pci-phy";
 		reg = <0x1e149000 0x0700>;
-		clocks = <&sysc MT7621_CLK_XTAL>;
+
 		#phy-cells = <1>;
+
+		clocks = <&sysc MT7621_CLK_XTAL>;
 	};
 
 	pcie2_phy: pcie-phy@...4a000 {
 		compatible = "mediatek,mt7621-pci-phy";
 		reg = <0x1e14a000 0x0700>;
-		clocks = <&sysc MT7621_CLK_XTAL>;
+
 		#phy-cells = <1>;
+
+		clocks = <&sysc MT7621_CLK_XTAL>;
 	};
 };
--