linux-kernel - Re: [PATCH 0/4] Add StarFive's StarLink-500 Cache Controller

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Message-ID: <20240317-viral-handcraft-12b2519ff1be@spud>
Date: Sun, 17 Mar 2024 15:01:05 +0000
From: Conor Dooley <conor@...nel.org>
To: Joshua Yeong <joshua.yeong@...rfivetech.com>
Cc: paul.walmsley@...ive.com, palmer@...belt.com, aou@...s.berkeley.edu,
	geert+renesas@...der.be, prabhakar.mahadev-lad.rj@...renesas.com,
	conor.dooley@...rochip.com, alexghiti@...osinc.com,
	evan@...osinc.com, ajones@...tanamicro.com, heiko@...ech.de,
	guoren@...nel.org, uwu@...nowy.me, jszhang@...nel.org,
	robh+dt@...nel.org, krzysztof.kozlowski+dt@...aro.org,
	conor+dt@...nel.org, leyfoon.tan@...rfivetech.com,
	jeeheng.sia@...rfivetech.com, linux-riscv@...ts.infradead.org,
	linux-kernel@...r.kernel.org, devicetree@...r.kernel.org
Subject: Re: [PATCH 0/4] Add StarFive's StarLink-500 Cache Controller

On Thu, Mar 14, 2024 at 02:12:01PM +0800, Joshua Yeong wrote:
> StarFive's StarLink-500 Cache Controller flush/invalidates cache using non-
> conventional CMO method. This driver provides the cache handling on StarFive
> RISC-V SoC.

Unlike the other "non-conventional" CMO methods, the jh8100 does not
pre-date the Zicbom extension. Why has that not been implemented?
How many peripherals on the jh8100 rely on non-coherent DMA?

Cheers,
Conor.

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