linux-kernel - Re: [PATCH v2 2/2] arm64: dts: qcom: sc8280xp: Describe the PCIe SMMUv3

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <phledylmdu23yrw6f4x7fkefntrejuwagazebsnkgyxsweodzg@pddhnc2gwexz>
Date: Sun, 17 Mar 2024 20:31:51 -0500
From: Bjorn Andersson <andersson@...nel.org>
To: Konrad Dybcio <konrad.dybcio@...aro.org>
Cc: Rob Herring <robh+dt@...nel.org>, 
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>, Conor Dooley <conor+dt@...nel.org>, 
	Will Deacon <will@...nel.org>, Robin Murphy <robin.murphy@....com>, 
	Joerg Roedel <joro@...tes.org>, Rob Herring <robh@...nel.org>, 
	Marijn Suijten <marijn.suijten@...ainline.org>, linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org, 
	linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org, iommu@...ts.linux.dev, 
	Johan Hovold <johan+linaro@...nel.org>
Subject: Re: [PATCH v2 2/2] arm64: dts: qcom: sc8280xp: Describe the PCIe
 SMMUv3

On Sat, Mar 09, 2024 at 02:31:10PM +0100, Konrad Dybcio wrote:
> SC8280XP actually has a third SMMU, which can be seen in e.g. the IORT
> ACPI table and is used for the PCIe hosts.
> 
> Unfortunately though, the secure firmware seems to be configured in a
> way such that Linux can't touch it, not even read back the ID registers.
> It also seems like the SMMU is configured to run in some sort of bypass
> mode, completely opaque to the OS.
> 
> Describe it so that one can configure it when running Linux as a
> hypervisor (e.g with [1]) and for hardware description completeness.
> 
> [1] https://github.com/TravMurav/slbounce
> Signed-off-by: Konrad Dybcio <konrad.dybcio@...aro.org>

Have this information been validated? Or are you suggesting we add it
for documentation purposes?

Regards,
Bjorn

> ---
>  arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> index a5b194813079..28edd30a9c04 100644
> --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> @@ -4648,6 +4648,22 @@ cci3_i2c1_sleep: cci3-i2c1-sleep-pins {
>  			};
>  		};
>  
> +		pcie_smmu: iommu@...80000 {
> +			compatible = "qcom,sc8280xp-smmu-v3", "arm,smmu-v3";
> +			reg = <0 0x14f80000 0 0x80000>;
> +			interrupts = <GIC_SPI 951 IRQ_TYPE_EDGE_RISING>,
> +				     <GIC_SPI 955 IRQ_TYPE_EDGE_RISING>,
> +				     <GIC_SPI 953 IRQ_TYPE_EDGE_RISING>;
> +			interrupt-names = "eventq",
> +					  "gerror",
> +					  "cmdq-sync";
> +			#iommu-cells = <1>;
> +			dma-coherent;
> +
> +			/* The hypervisor prevents register access from Linux */
> +			status = "reserved";
> +		};
> +
>  		apps_smmu: iommu@...00000 {
>  			compatible = "qcom,sc8280xp-smmu-500", "arm,mmu-500";
>  			reg = <0 0x15000000 0 0x100000>;
> 
> -- 
> 2.44.0
>