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Message-ID: <87wmpziy9q.ffs@tglx>
Date: Mon, 18 Mar 2024 12:18:25 +0100
From: Thomas Gleixner <tglx@...utronix.de>
To: Christophe JAILLET <christophe.jaillet@...adoo.fr>, Tianyang Zhang
<zhangtianyang@...ngson.cn>, chenhuacai@...nel.org,
jiaxun.yang@...goat.com
Cc: linux-mips@...r.kernel.org, linux-kernel@...r.kernel.org, Baoqi Zhang
<zhangbaoqi@...ngson.cn>, Biao Dong <dongbiao@...ngson.cn>
Subject: Re: [PATCH V2] irqchip/loongson-pch-pic: Update interrupt
registration policy
On Sat, Mar 16 2024 at 15:03, Christophe JAILLET wrote:
> Le 16/03/2024 à 09:21, Tianyang Zhang a écrit :
>> @@ -171,6 +183,27 @@ static int pch_pic_domain_translate(struct irq_domain *d,
>> return -EINVAL;
>>
>> *hwirq = fwspec->param[0] - priv->gsi_base;
>> +
>> + raw_spin_lock_irqsave(&priv->pic_lock, flags);
>> + /* Check pic-table to confirm if the hwirq has been assigned */
>> + for (i = 0; i < priv->inuse; i++) {
>> + if (priv->table[i] == *hwirq) {
>> + *hwirq = i;
>> + break;
>> + }
>> + }
>> + if (i == priv->inuse) {
>> + /* Assign a new hwirq in pic-table */
>> + if (priv->inuse >= PIC_COUNT) {
>> + pr_err("pch-pic domain has no free vectors\n");
>> + raw_spin_unlock_irqrestore(&priv->pic_lock, flags);
>> + return -EINVAL;
>> + }
>> + priv->table[priv->inuse] = *hwirq;
>> + *hwirq = priv->inuse++;
>> + }
>> + raw_spin_unlock_irqrestore(&priv->pic_lock, flags);
>
> Hi,
>
> not sure if it helps or if this is a hot path, but, IIUC, taking the
> lock could be avoided with some code reordering and 'inuse' being an
> atomic_t.
It's the translate and setup path, so nothing to optimize here.
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