linux-kernel - RE: [PATCH v4 5/6] dt-bindindgs: clock: nxp: support i.MX95 Display CSR module

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Date: Mon, 18 Mar 2024 12:37:34 +0000
From: Peng Fan <peng.fan@....com>
To: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>, "Peng Fan (OSS)"
	<peng.fan@....nxp.com>, Abel Vesa <abelvesa@...nel.org>, Michael Turquette
	<mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>, Rob Herring
	<robh@...nel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
	Conor Dooley <conor+dt@...nel.org>, Shawn Guo <shawnguo@...nel.org>, Sascha
 Hauer <s.hauer@...gutronix.de>, Pengutronix Kernel Team
	<kernel@...gutronix.de>, Fabio Estevam <festevam@...il.com>
CC: "linux-clk@...r.kernel.org" <linux-clk@...r.kernel.org>,
	"imx@...ts.linux.dev" <imx@...ts.linux.dev>, "devicetree@...r.kernel.org"
	<devicetree@...r.kernel.org>, "linux-arm-kernel@...ts.infradead.org"
	<linux-arm-kernel@...ts.infradead.org>, "linux-kernel@...r.kernel.org"
	<linux-kernel@...r.kernel.org>
Subject: RE: [PATCH v4 5/6] dt-bindindgs: clock: nxp: support i.MX95 Display
 CSR module

> Subject: Re: [PATCH v4 5/6] dt-bindindgs: clock: nxp: support i.MX95 Display
> CSR module
> 
> On 14/03/2024 14:25, Peng Fan (OSS) wrote:
> > From: Peng Fan <peng.fan@....com>
> >
> > The DISPLAY_CSR provides control and status of the following:
> >  Clock selection for the Display Engines  Pixel Interleaver mode
> > selection  Pixel Link enables  QoS settings for the display controller
> > ArCache and AwCache signals  Display Engine plane association
> >
> > This patch is to add the clock features for this module
> >
> > Signed-off-by: Peng Fan <peng.fan@....com>
> > ---
> >  .../bindings/clock/nxp,imx95-display-csr.yaml      | 50
> ++++++++++++++++++++++
> >  include/dt-bindings/clock/nxp,imx95-clock.h        |  4 ++
> >  2 files changed, 54 insertions(+)
> >
> > diff --git
> > a/Documentation/devicetree/bindings/clock/nxp,imx95-display-csr.yaml
> > b/Documentation/devicetree/bindings/clock/nxp,imx95-display-csr.yaml
> > new file mode 100644
> > index 000000000000..9a5e21346b0d
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/clock/nxp,imx95-display-csr.ya
> > +++ ml
> > @@ -0,0 +1,50 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > +---
> > +$id:
> > +https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi
> > +cetree.org%2Fschemas%2Fclock%2Fnxp%2Cimx95-display-
> csr.yaml%23&data=0
> >
> +5%7C02%7Cpeng.fan%40nxp.com%7C479f8c47bd4d421a669708dc45316f1
> 2%7C686e
> >
> +a1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C638461325839625184%7
> CUnknown%7
> >
> +CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haW
> wiLCJX
> >
> +VCI6Mn0%3D%7C0%7C%7C%7C&sdata=rntSlDs8ASXSb3L%2F9ZCzgW%2Bzo
> v2LU9vcTD7
> > +SvjE37Nw%3D&reserved=0
> > +$schema:
> > +https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi
> > +cetree.org%2Fmeta-
> schemas%2Fcore.yaml%23&data=05%7C02%7Cpeng.fan%40nx
> >
> +p.com%7C479f8c47bd4d421a669708dc45316f12%7C686ea1d3bc2b4c6fa9
> 2cd99c5c
> >
> +301635%7C0%7C0%7C638461325839637072%7CUnknown%7CTWFpbGZs
> b3d8eyJWIjoiM
> >
> +C4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C0%7
> C%7C%7
> >
> +C&sdata=%2BjYpR8p7IDjRzV39hJhtv8FozALx9HqqLhoFgwBJCm4%3D&reserv
> ed=0
> > +
> > +title: NXP i.MX95 Display Block Control
> > +
> > +maintainers:
> > +  - Peng Fan <peng.fan@....com>
> > +
> > +properties:
> > +  compatible:
> > +    items:
> > +      - const: nxp,imx95-display-csr
> > +      - const: syscon
> 
> Why do you create five different bindings with almost the same contents?
> Do you plan to grow on them, like add more compatibles here? Otherwise all
> this could be in one binding.

The blk ctrls are for different functions.

We may expand the bindings to add more properties for the blk ctrls, but I
am not sure as of now. I could merge them into one binding except
the one with mux-controller if you prefer. Or leave them as is, still
separate binding files.

Thanks,
Peng.

> 
> Best regards,
> Krzysztof