linux-kernel - Re: [PATCH] mediatek: dsi: Correct calculation formula of PHY Timing

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Date: Wed, 20 Mar 2024 06:28:25 +0000
From: CK Hu (胡俊光) <ck.hu@...iatek.com>
To: Shuijing Li (李水静) <Shuijing.Li@...iatek.com>,
	"chunkuang.hu@...nel.org" <chunkuang.hu@...nel.org>,
	Jitao Shi (石记涛) <jitao.shi@...iatek.com>,
	"daniel@...ll.ch" <daniel@...ll.ch>, "p.zabel@...gutronix.de"
	<p.zabel@...gutronix.de>, "airlied@...il.com" <airlied@...il.com>,
	"matthias.bgg@...il.com" <matthias.bgg@...il.com>,
	"angelogioacchino.delregno@...labora.com"
	<angelogioacchino.delregno@...labora.com>
CC: "dri-devel@...ts.freedesktop.org" <dri-devel@...ts.freedesktop.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"linux-mediatek@...ts.infradead.org" <linux-mediatek@...ts.infradead.org>,
	"linux-arm-kernel@...ts.infradead.org"
	<linux-arm-kernel@...ts.infradead.org>, Project_Global_Chrome_Upstream_Group
	<Project_Global_Chrome_Upstream_Group@...iatek.com>
Subject: Re: [PATCH] mediatek: dsi: Correct calculation formula of PHY Timing

Hi, Shuijing:

On Fri, 2024-03-15 at 15:29 +0800, Shuijing Li wrote:
> This patch correct calculation formula of PHY timing.
> Make actual phy timing more accurate.

Please define what is accurate and how much this patch improve. For
example, the spec define event 2 happen after event 1 and the duration
between event 1 and event 2 should be from 50us to 100us. But current
duration is 60us and is near the boundary. So this patch make the
duration to 70us so it is near the safe range.

Regards,
CK

> 
> Signed-off-by: Shuijing Li <shuijing.li@...iatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_dsi.c | 33 +++++++++++++++-------------
> --
>  1 file changed, 17 insertions(+), 16 deletions(-)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
> b/drivers/gpu/drm/mediatek/mtk_dsi.c
> index a2fdfc8ddb15..d1bd7d671880 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> @@ -235,22 +235,23 @@ static void mtk_dsi_phy_timconfig(struct
> mtk_dsi *dsi)
>  	u32 data_rate_mhz = DIV_ROUND_UP(dsi->data_rate, 1000000);
>  	struct mtk_phy_timing *timing = &dsi->phy_timing;
>  
> -	timing->lpx = (60 * data_rate_mhz / (8 * 1000)) + 1;
> -	timing->da_hs_prepare = (80 * data_rate_mhz + 4 * 1000) / 8000;
> -	timing->da_hs_zero = (170 * data_rate_mhz + 10 * 1000) / 8000 +
> 1 -
> -			     timing->da_hs_prepare;
> -	timing->da_hs_trail = timing->da_hs_prepare + 1;
> -
> -	timing->ta_go = 4 * timing->lpx - 2;
> -	timing->ta_sure = timing->lpx + 2;
> -	timing->ta_get = 4 * timing->lpx;
> -	timing->da_hs_exit = 2 * timing->lpx + 1;
> -
> -	timing->clk_hs_prepare = 70 * data_rate_mhz / (8 * 1000);
> -	timing->clk_hs_post = timing->clk_hs_prepare + 8;
> -	timing->clk_hs_trail = timing->clk_hs_prepare;
> -	timing->clk_hs_zero = timing->clk_hs_trail * 4;
> -	timing->clk_hs_exit = 2 * timing->clk_hs_trail;
> +	timing->lpx = (80 * data_rate_mhz / (8 * 1000)) + 1;
> +	timing->da_hs_prepare = (59 * data_rate_mhz + 4 * 1000) / 8000
> + 1;
> +	timing->da_hs_zero = (163 * data_rate_mhz + 11 * 1000) / 8000 +
> 1 -
> +		timing->da_hs_prepare;
> +	timing->da_hs_trail = (78 * data_rate_mhz + 7 * 1000) / 8000 +
> 1;
> +
> +	timing->ta_go = 4 * timing->lpx;
> +	timing->ta_sure = 3 * timing->lpx / 2;
> +	timing->ta_get = 5 * timing->lpx;
> +	timing->da_hs_exit = (118 * data_rate_mhz / (8 * 1000)) + 1;
> +
> +	timing->clk_hs_prepare = (57 * data_rate_mhz / (8 * 1000)) + 1;
> +	timing->clk_hs_post = (65 * data_rate_mhz + 53 * 1000) / 8000 +
> 1;
> +	timing->clk_hs_trail = (78 * data_rate_mhz + 7 * 1000) / 8000 +
> 1;
> +	timing->clk_hs_zero = (330 * data_rate_mhz / (8 * 1000)) + 1 -
> +		timing->clk_hs_prepare;
> +	timing->clk_hs_exit = (118 * data_rate_mhz / (8 * 1000)) + 1;
>  
>  	timcon0 = timing->lpx | timing->da_hs_prepare << 8 |
>  		  timing->da_hs_zero << 16 | timing->da_hs_trail << 24;