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Message-ID: <ZfqstNocte2wV_ad@shikoro>
Date: Wed, 20 Mar 2024 10:30:28 +0100
From: Wolfram Sang <wsa+renesas@...g-engineering.com>
To: Prabhakar <prabhakar.csengg@...il.com>
Cc: Geert Uytterhoeven <geert+renesas@...der.be>,
Chris Brandt <chris.brandt@...esas.com>,
Andi Shyti <andi.shyti@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>,
Magnus Damm <magnus.damm@...il.com>,
linux-renesas-soc@...r.kernel.org, linux-i2c@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
Fabrizio Castro <fabrizio.castro.jz@...esas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>,
Rob Herring <robh@...nel.org>
Subject: Re: [PATCH v3 1/4] dt-bindings: i2c: renesas,riic: Document
R9A09G057 support
On Tue, Mar 19, 2024 at 01:25:00PM +0000, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
>
> Document support for the I2C Bus Interface (RIIC) available in the
> Renesas RZ/V2H(P) (R9A09G057) SoC.
>
> The RIIC interface in the Renesas RZ/V2H(P) differs from RZ/A in a
> couple of ways:
> - Register offsets for the RZ/V2H(P) SoC differ from those of the
> RZ/A SoC.
> - RZ/V2H register access is limited to 8-bit, whereas RZ/A supports
> 8/16/32-bit.
> - RZ/V2H has bit differences in the slave address register.
>
> To accommodate these differences, a new compatible string
> "renesas,riic-r9a09g057" is added.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@...der.be>
> Acked-by: Rob Herring <robh@...nel.org>
Reviewed-by: Wolfram Sang <wsa+renesas@...g-engineering.com>
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