linux-kernel - RE: [PATCH 0/4] Add StarFive's StarLink-500 Cache Controller

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Message-ID:
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Date: Fri, 22 Mar 2024 06:16:21 +0000
From: Joshua Yeong <joshua.yeong@...rfivetech.com>
To: Conor Dooley <conor.dooley@...rochip.com>, Conor Dooley <conor@...nel.org>
CC: "paul.walmsley@...ive.com" <paul.walmsley@...ive.com>,
	"palmer@...belt.com" <palmer@...belt.com>, "aou@...s.berkeley.edu"
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	"conor+dt@...nel.org" <conor+dt@...nel.org>, Leyfoon Tan
	<leyfoon.tan@...rfivetech.com>, JeeHeng Sia <jeeheng.sia@...rfivetech.com>,
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Subject: RE: [PATCH 0/4] Add StarFive's StarLink-500 Cache Controller

Hi Conor,

> -----Original Message-----
> From: Conor Dooley <conor.dooley@...rochip.com>
> Sent: Wednesday, March 20, 2024 4:09 PM
> To: Conor Dooley <conor@...nel.org>
> Cc: Joshua Yeong <joshua.yeong@...rfivetech.com>;
> paul.walmsley@...ive.com; palmer@...belt.com; aou@...s.berkeley.edu;
> geert+renesas@...der.be; prabhakar.mahadev-lad.rj@...renesas.com;
> alexghiti@...osinc.com; evan@...osinc.com; ajones@...tanamicro.com;
> heiko@...ech.de; guoren@...nel.org; uwu@...nowy.me;
> jszhang@...nel.org; robh+dt@...nel.org; krzysztof.kozlowski+dt@...aro.org;
> conor+dt@...nel.org; Leyfoon Tan <leyfoon.tan@...rfivetech.com>; JeeHeng
> Sia <jeeheng.sia@...rfivetech.com>; linux-riscv@...ts.infradead.org; linux-
> kernel@...r.kernel.org; devicetree@...r.kernel.org
> Subject: Re: [PATCH 0/4] Add StarFive's StarLink-500 Cache Controller
> 
> On Sun, Mar 17, 2024 at 03:01:05PM +0000, Conor Dooley wrote:
> > On Thu, Mar 14, 2024 at 02:12:01PM +0800, Joshua Yeong wrote:
> > > StarFive's StarLink-500 Cache Controller flush/invalidates cache
> > > using non- conventional CMO method. This driver provides the cache
> > > handling on StarFive RISC-V SoC.
> >
> > Unlike the other "non-conventional" CMO methods, the jh8100 does not
> > pre-date the Zicbom extension. Why has that not been implemented?
> 
> Stefan pointed out on IRC yesterday that one of the main selling points is the
> ease of operating on large ranges.
> 
> > How many peripherals on the jh8100 rely on non-coherent DMA?

JH8100 integrates in-house matured/stable CPU but it is a bit dated today.
However, our newer generation of CPU should already support this extension.

Most of the peripherals are coherent except mainly multimedia peripheral.

Regards,
Joshua

> >
> > Cheers,
> > Conor.
>