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Message-Id: <20240322063930.749126-5-xu.yang_2@nxp.com>
Date: Fri, 22 Mar 2024 14:39:27 +0800
From: Xu Yang <xu.yang_2@....com>
To: frank.li@....com,
will@...nel.org,
mark.rutland@....com,
robh+dt@...nel.org,
krzysztof.kozlowski+dt@...aro.org,
conor+dt@...nel.org,
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Cc: mike.leach@...aro.org,
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mingo@...hat.com,
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imx@...ts.linux.dev
Subject: [PATCH v8 5/8] perf: imx_perf: fix counter start and config sequence
In current driver, the counter will start firstly and then be configured.
This sequence is not correct for AXI filter events since the correct
AXI_MASK and AXI_ID are not set yet. Then the results may be inaccurate.
Fixes: 55691f99d417 ("drivers/perf: imx_ddr: Add support for NXP i.MX9 SoC DDRC PMU driver")
cc: <stable@...r.kernel.org>
Signed-off-by: Xu Yang <xu.yang_2@....com>
---
Changes in v5:
- new patch
Changes in v6:
- no changes
Changes in v7:
- no changes
Changes in v8:
- add fix tag
---
drivers/perf/fsl_imx9_ddr_perf.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/perf/fsl_imx9_ddr_perf.c b/drivers/perf/fsl_imx9_ddr_perf.c
index 011377c01dea..fab6596d3e28 100644
--- a/drivers/perf/fsl_imx9_ddr_perf.c
+++ b/drivers/perf/fsl_imx9_ddr_perf.c
@@ -539,12 +539,12 @@ static int ddr_perf_event_add(struct perf_event *event, int flags)
hwc->idx = counter;
hwc->state |= PERF_HES_STOPPED;
- if (flags & PERF_EF_START)
- ddr_perf_event_start(event, flags);
-
/* read trans, write trans, read beat */
imx93_ddr_perf_monitor_config(pmu, event_id, counter, cfg1, cfg2);
+ if (flags & PERF_EF_START)
+ ddr_perf_event_start(event, flags);
+
return 0;
}
--
2.34.1
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