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Message-ID: <CAFULd4aR_zmUneh=3RKHnbT=8Fc_kCkLHs54aUVjfXoAJdXdGQ@mail.gmail.com>
Date: Fri, 22 Mar 2024 07:51:45 +0100
From: Uros Bizjak <ubizjak@...il.com>
To: Waiman Long <longman@...hat.com>
Cc: linux-kernel@...r.kernel.org, Peter Zijlstra <peterz@...radead.org>,
Ingo Molnar <mingo@...hat.com>, Will Deacon <will@...nel.org>, Boqun Feng <boqun.feng@...il.com>
Subject: Re: [PATCH] locking/qspinlock: Use atomic_try_cmpxchg_relaxed() in xchg_tail()
On Fri, Mar 22, 2024 at 12:52 AM Waiman Long <longman@...hat.com> wrote:
>
> On 3/21/24 15:52, Uros Bizjak wrote:
> > Use atomic_try_cmpxchg_relaxed(*ptr, &old, new) instead of
> > atomic_cmpxchg_relaxed (*ptr, old, new) == old in xchg_tail().
> > x86 CMPXCHG instruction returns success in ZF flag,
> > so this change saves a compare after cmpxchg.
> >
> > No functional change intended.
> >
> > Signed-off-by: Uros Bizjak <ubizjak@...il.com>
> > Cc: Peter Zijlstra <peterz@...radead.org>
> > Cc: Ingo Molnar <mingo@...hat.com>
> > Cc: Will Deacon <will@...nel.org>
> > Cc: Waiman Long <longman@...hat.com>
> > Cc: Boqun Feng <boqun.feng@...il.com>
> > ---
> > kernel/locking/qspinlock.c | 13 +++++--------
> > 1 file changed, 5 insertions(+), 8 deletions(-)
> >
> > diff --git a/kernel/locking/qspinlock.c b/kernel/locking/qspinlock.c
> > index ebe6b8ec7cb3..1df5fef8a656 100644
> > --- a/kernel/locking/qspinlock.c
> > +++ b/kernel/locking/qspinlock.c
> > @@ -220,21 +220,18 @@ static __always_inline void clear_pending_set_locked(struct qspinlock *lock)
> > */
> > static __always_inline u32 xchg_tail(struct qspinlock *lock, u32 tail)
> > {
> > - u32 old, new, val = atomic_read(&lock->val);
> > + u32 old, new;
> >
> > - for (;;) {
> > - new = (val & _Q_LOCKED_PENDING_MASK) | tail;
> > + old = atomic_read(&lock->val);
> > + do {
> > + new = (old & _Q_LOCKED_PENDING_MASK) | tail;
> > /*
> > * We can use relaxed semantics since the caller ensures that
> > * the MCS node is properly initialized before updating the
> > * tail.
> > */
> > - old = atomic_cmpxchg_relaxed(&lock->val, val, new);
> > - if (old == val)
> > - break;
> > + } while (!atomic_try_cmpxchg_relaxed(&lock->val, &old, new));
> >
> > - val = old;
> > - }
> > return old;
> > }
> > #endif /* _Q_PENDING_BITS == 8 */
>
> LGTM, note that this xchg_tail() variant is not used in all the distros
> that I am aware of as it requires NR_CPUS >= 16k.
Yes, I am aware of this. I have tested the patch simply by
unconditionally setting _Q_PENDING_BITS to 1 in
include/asm-generic/qspinlock_types.h.
>
> Reviewed-by: Waiman Long <longman@...hat.com>
Thanks,
Uros.
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