linux-kernel - [PATCH v1 1/1] phy: freescale: imx8m-pcie: fix pcie link-up instability

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Message-ID: <20240322130646.1016630-2-marcel@ziswiler.com>
Date: Fri, 22 Mar 2024 14:06:32 +0100
From: Marcel Ziswiler <marcel@...wiler.com>
To: linux-phy@...ts.infradead.org
Cc: linux-imx@....com,
	Lucas Stach <l.stach@...gutronix.de>,
	linux-arm-kernel@...ts.infradead.org,
	kernel@...gutronix.de,
	Richard Zhu <hongxing.zhu@....com>,
	linux-kernel@...r.kernel.org,
	Marcel Ziswiler <marcel.ziswiler@...adex.com>,
	Fabio Estevam <festevam@...il.com>,
	Heiko Stuebner <heiko@...ech.de>,
	Kishon Vijay Abraham I <kishon@...nel.org>,
	Marc Kleine-Budde <mkl@...gutronix.de>,
	Rob Herring <robh@...nel.org>,
	Sascha Hauer <s.hauer@...gutronix.de>,
	Shawn Guo <shawnguo@...nel.org>,
	Tim Harvey <tharvey@...eworks.com>,
	Vinod Koul <vkoul@...nel.org>,
	Yang Li <yang.lee@...ux.alibaba.com>,
	imx@...ts.linux.dev
Subject: [PATCH v1 1/1] phy: freescale: imx8m-pcie: fix pcie link-up instability

From: Marcel Ziswiler <marcel.ziswiler@...adex.com>

Leaving AUX_PLL_REFCLK_SEL at its reset default of AUX_IN (PLL clock)
proves to be more stable on the i.MX 8M Mini.

Fixes: 1aa97b002258 ("phy: freescale: pcie: Initialize the imx8 pcie standalone phy driver")

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@...adex.com>
---

 drivers/phy/freescale/phy-fsl-imx8m-pcie.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
index b700f52b7b67..11fcb1867118 100644
--- a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
+++ b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
@@ -110,8 +110,10 @@ static int imx8_pcie_phy_power_on(struct phy *phy)
 		/* Source clock from SoC internal PLL */
 		writel(ANA_PLL_CLK_OUT_TO_EXT_IO_SEL,
 		       imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG062);
-		writel(AUX_PLL_REFCLK_SEL_SYS_PLL,
-		       imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG063);
+		if (imx8_phy->drvdata->variant != IMX8MM) {
+			writel(AUX_PLL_REFCLK_SEL_SYS_PLL,
+			       imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG063);
+		}
 		val = ANA_AUX_RX_TX_SEL_TX | ANA_AUX_TX_TERM;
 		writel(val | ANA_AUX_RX_TERM_GND_EN,
 		       imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG064);
--
2.44.0